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 From Nand to Tetris - the Elements of Computing Systems 
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Joined: Mon Aug 14, 2017 8:23 am
Posts: 157
N2T has been mentioned several times on this forum, but it is certainly relevant with the recent interest in TTL computers.

In 2013, I came across the N2T course and bought the book "The Elements of Computer Systems" and embarked on studying the simple 16-bit "Hack" computer design. I thought about implementing all of the logic in 74xx00 quad nand gates - and this led to a bitslice design, with 20off 74xx00 surface mount nand gate packages mounted on a 5cm x 5cm board for each bitslice. In addition to the bitslice boards, a control unit and ROM and RAM would be needed.


My inspiration for the bitslice came from the PDP-8 - where they managed to package the principal registers Address, Data and PC onto one module and an adder/accumulator onto another. The early PDP-8 was a diode transistor logic design - using about 10 cheap diodes for every expensive transistor.

Whilst designing the bitslice, I found that there were three frequently occurring logic structures:

1. 2 input Exclusive OR gate - made from four 2 input nands
2. 2:1 data selector - again four 2 input nands
3. D-type flip flop - made from five 2 input nands.

Whilst I did a trial layout of the bitslice pcb - it was never sent to manufacture, and I got distracted with other things, such as the Gigatron - which offered a far more painless entry route into TTL computers.


However, over the last few days I have been thinking about logic implementations and had a look at what options are available. Unfortunately the last of the register files - the 4x4bit 74xx670 has now reached the point of obsolescence, and there seems to be no easy way to efficiently recreate it in more readily available TTL.

I then remembered Dr. Jeffyl's post about tiny gate (74LVC1G) TTL logic, that is small, very fast and low power, and has a number of flip flop types available. I noticed that the output selector structure on the 74xx670 is very much like a 74xx153 quad multiplexer - so there may be a possibility of building register files from tiny gate flip flops and 74xx153 devices.


The idea of building up a cpu from tiny gate logic got me thinking again about the 3 principal structures used in the "Hack" bitslice - and all of them are available as tiny gates. This would mean that the bitslice would be reduced from 20 off, 14 pin nand packages to about 24 tiny gates. This reduction in package size would allow the Hack 16 bit computer to be built on two 10x10cm boards - one containing ROM, RAM and control unit, and one containing all the bitslice logic.

Food for thought,


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Last edited by monsonite on Wed Mar 27, 2019 5:40 pm, edited 2 times in total.

Tue Mar 26, 2019 11:26 pm

Joined: Wed Apr 24, 2013 9:40 pm
Posts: 206
Location: Huntsville, AL
Too much food for thought. :)

Michael A.

Wed Mar 27, 2019 1:55 am

Joined: Mon Aug 14, 2017 8:23 am
Posts: 157
I have replaced the low resolution screen-shot of the Hack Bitslice with the following PDF:



The ALU has two inputs which can be set to zero with control signals ZX and ZY (IC5, IC6) and also inverted/negated with NX and NY (IC3, IC4)

After zero and negation, the inputs enter a full adder (IC1, IC2), and then a 2 input MUX (IC9) which allows selection between the adder SUM output or the AND output of X and Y. IC10 allows the negation of the output and IC16 detects if the output is zero.

This combination of an ADD operation, or alternatively an AND operation allows a wide variety of functions to be derived - especially when used with selective zeroing and negation of the inputs and negation of the output (NO).

Whilst being flexible, it does require 6 control inputs (ZX, ZY, NX, NY, F, NO and Carry In). It is also a ripple carry adder - so the maximum speed of execution will be dictated by the carry propagation time, and the propagation delay of the gates used.

Address and Data Multiplexers

IC7 forms a 2 input multiplexer - allowing the selection between the memory or the data register to form the Y input to the ALU.

IC8 selects between the output of the ALU or output from the ROM to be used as the input to the address register.

Address and Data Registers

The Hack design has an address register (AREG) and a data register (DREG) - generally known as the accumulator. These registers consist of a D-type flip flop preceded by a 2 input data selector. You can either accept a new input or regenerate the previous register output. The logic here is similar to a 74xx377, which allows the Q output of the flip flop to be recirculated back to the D input via a 2 input mux - see below.


Program Counter

The Program Counter is a similar D flip flop (IC19) preceded with logic to allow it to be loaded from the address register via IC18, incremented by 1 by IC13 or reset.

Hack is a fairly simple accumulator based machine aimed at teaching the principles of cpus. It lacks the elegant addressing modes that make the coding easier. However it could be constructed in bitslice form, creating a machine of similar complexity to the PDP-8.

With instruction decoding and memory access the design would be about 1600 nand gates (400 packages).

Choosing 74xx86 quad XOR, 74xx157 data selectors, 74xx377 octal registers and 74xx283 4-bit adder would reduce the package count considerably.

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Wed Mar 27, 2019 5:42 pm

Joined: Fri May 05, 2017 7:39 pm
Posts: 22
Never dived deeply into such matter. It's astonishes me what can be done with such constraints - yes, yes, it is just logic :D .

Now I can understand much better how the Apollo navigation guidance computer might be realized - all 3 input NORs IIRC.

Thank you for the PDF!


Wed Mar 27, 2019 7:13 pm

Joined: Mon Aug 14, 2017 8:23 am
Posts: 157
Now I can understand much better how the Apollo navigation guidance computer might be realized - all 3 input NORs IIRC.

Hi Arne - it was the Apollo Guidance computer that first set me off on this journey. I was intrigued how a complex machine could just be made from simple logic - provided that you had either NAND or NOR.

These days, building computers from just 74xx00 quad nand gates is just bonkers, there are much better ways, but I had to go through the paper exercise of the Bitslice to see just what was involved. It taught me that there are basically three important structures, XOR gates, 2:1 data selectors and D-type flip flops - plus a few nands as glue logic. With those basic elements you can build almost anything. The big advantage we have these days is access to large, high speed ROMs and RAMs, which makes recreating a TTL computer from scratch so much easier. But it's not just hardware that has progressed in our favour - we can simulate and emulate new architectures at reasonable speed with a few lines of Python or C code.

The first PDP-8 machines predated TTL by about 5 years and were built using Diode Transistor logic. Suitable transistors were very expensive - the equivalent of $20 today. This means that they were used very sparingly for flip flops, or for gates that required inversion. Most of the logic was implemented in diodes - that were much cheaper. Every trick in the book was used to reduce the transistor count in the PDP-8. The final total was 1409 transistors and 10,148 diodes in the early PDP-8. The schematics for the registers and the alu bitslices can be found here:

The R211 board carried the Memory Address (MA), Memory Buffer (MB) and Program Counter (PC). It was only 13 transistors and 137 diodes. You can find it here: ... 1/mode/1up

The R210 Accumulator/ ALU bitslice was similar - 12 transistors and 123 diodes.

If you wish to look at these 50 year old schematics - and carefully transcribed modern EagleCAD board layouts - you can find them here. With this you could build your own faithful 1965 PDP-8 replica.

But there's always easier ways, software simulation, modern TTL replica or FPGA recreation.



Last edited by monsonite on Wed Mar 27, 2019 8:26 pm, edited 1 time in total.

Wed Mar 27, 2019 8:20 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1647
Highly interesting!

Wed Mar 27, 2019 8:25 pm

Joined: Fri May 05, 2017 7:39 pm
Posts: 22
Hi Ken,

thank you for this plethora of information! That is really brilliant work.

I remember I once stumbled across old schematics of the PDP-8. It requires some (hmm, quite a lot) time to become familiar with these odd old symbols. And there were no data sheets for the used semiconductors. With much suggestion and assumption I get an idea of how things might worked. Looking at -- so much efforts - Kudos!

When I first read your opening post I thought: that's not my taste - too much effort in relation to the gain. But now ... looking at these DTL-gates ... thinking of diodes in a 0603 or 0402 case and SOT-23 or -89 transistors ... need to check thermal budgets ... could be funny ... :D ... perhaps in a few years ... there is still a set of IM6400/6401/6402 together with some 65X11 RAMs and 6531 EPROMs lurking in one drawer ... never found a burner for these ...


Thu Mar 28, 2019 12:29 am

Joined: Mon Aug 14, 2017 8:23 am
Posts: 157
Hi Arne,

I agree, the PDP-8 schematics are quite difficult to interpret.

You can pick out the basic flip-flops, but it's the vast amounts of surrounding diode steering logic which really confuses the newcomer. It doesn't help that it it is all based on PNP devices with negative supply rails to further obfuscate what is happening.

If I recall, DEC created their own set of logic symbols, because there were no standards at that time. Some of these probably arose from Ken Olsen's involvement with the TX2 at MIT.

I had a look at creating some DTL gates - using modern NPN transistors and dual-diodes in SOT-23 SMT packages. My results were not spectacular, with a maximum clock frequency of around 1MHz. It was my lack of success in getting a DTL flip-flop to work reliably - that caused me to look further at TTL.

There is one home cpu project that documents using home made DTL gates -


Thu Mar 28, 2019 8:31 am
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