The bit serial project progresses slowly - due to a number of "schoolboy errors".

I loaded two sets of sequence data into the ROMs and started the simulation - in this case adding pairs of 8-bit numbers. All appeared to be going well for the first couple of additions but then things rapidly went AWOL.

I thought it was a timing problem with my sequencers, but eventually realised that I had my bit-ordering as MSB first and not LSB first!

I quickly edited the order in which the shift registers connect to the ROMS and the serial adder sprang into life - successfully processing the ROM data.

I then thought I would try subtraction, which involves negating one of the bit serial streams - which is easily done with a 2-input XOR that sits just in front of the ALU, and adding 1 to the negated stream - which means setting the Carry-in for the first bit period of the serial stream.

This was done manually for both streams in turn allowing me to test both (A-B) and (B-A) giving the correct results for each test case.

I am now working out a simple circuit which automates the carry input to be set for the first bit-period. Within the bit-counter circuit I have a 3 to 8 line decoder (74xx138) This gives me a set of 8 individual low going pulses co-timed with all of the bits in the packet. If the carry in needs to be set for just Bit 0, I can use the first of these sequenced outputs to force a carry into the adder in the right time slot.

The ALU is intended to have the following instructions:

ADD
SUB
ADC
SBB
AND
OR
XOR
NEG/INV

It would also be beneficial if it had and INC (+1) and a DEC (-1) or perhaps a more generic case of ADD n and SUB n - where n is a short constant. These instructions are useful for modifying the PC for intra-page jumps and modifying the stack pointer during PUSH and POP operations.

The other feature I have designed tonight is a toggle switch entry and digit display system - in otherwords a poorrman's front panel. A row of 8 push buttons are used to toggle between high and low states, allowing an 8-bit word to be constructed within the switch register.

The word is displayed on LEDs in binary and 7 segment display in hex format.

This facility will make it a lot easier to enter test data, or short programs into memory. And as we all know - it's not a real computer without a front panel!

Tomorrow I hope to work on the logic that decodes the instructions and controls the ALU. The aim is to have some sort of a primitive (2 function) calculator working first and this can be augmented into a stored program machine in a series of steps.

My inspiration for this project comes from early bit serial machines such as the PDP-8/S, the Wireless World Computer (Aug-Dec 1967) and the Kenbak-1.

I will include an interim design on my github repository, and it can be exercised using H. Neeman's "Digital" simulator.

The IC package count is 15 TTL parts and 2 EPROMS. This includes the toggle switch numerical entry and a 2 register output monitor.

My experimental bit serial ALU is now available to view using "Digital" from my Github repository

https://github.com/monsonite/Bit_Serial

Here is the circuit description for the latest design.

Circuit Description.

Bit Counter and Bit Time Decoder

The heart of the machine is a free running  4-bit counter IC1 (74xx161)which is used to keep track of the individual bits within the serial bit-packet.  The QA, QB and QC outputs of this bit-counter feed the inputs of a 3 to 8 line decoder IC2 (74x138). The decoder provides individual low going outputs, which are used to control specific events within the time-frame of the bit-packet.

Program Counter

IC3 and IC4 are also 4-bit counters (74xx161) which are chained together to create an 8-bit Program Counter. The program counter is incremented by a positive pulse derived from IC2 output /Y7.  In this experimental architecture the PC is only 8-bits and can address 256 bytes of memory. It could easily be extended to 12 or 16-bits to address 4K or 64K bytes of memory.

The PC has the means to accept a parallel load, which will effectively cause it to jump to a new address supplied via the parallel load.  Shift register IC17 (74xx164) acts as an Address Register and can supply the jump address to the Program Counter.

ROM Addressing and serial conversion

In the experimental circuit, the PC adresses two 2K ROMs  IC5 and IC6.  These ROMs allow two separate streams of stored data to be generated for test purposes. This data is converted from parallel to serial by shift registers  IC6 and IC8 (74xx166).  These registers can be used to feed data into the serial ALU to allow arithmetical or logical operations to be performed on it.  These registers are loaded using a signal from the bit-time decoder IC2 output  /Y0 - meaning that the registers are updated synchronously with the start of the serial packet Bit_0.

Bit Serial ALU

The bit serial ALU is based on quad XOR gates IC9 (74xx86) and quad NAND gates IC10 (74xx00). The XOR and NAND gates are configured as a full-adder, with a further 2 XOR gates at its A and B inputs to allow one or both inputs to be negated (1's complement). This allows subtraction, inversion and several other logical functions to be created.

A is considered to be the Accumulator and B is the source of the other 8-bit operand, supplied from memory. The ALU is capable of the following functions on opearands A and B:

ADD
SUB
ADC  add with carry
SBB  subtract with borrow
AND
OR
XOR
NEG    1's complement
INC      Add 1  (or any other short constant)
DEC    Subtract 1 (or any other short constant)

The full adder has inputs for the operands A and B and also a Carry input Cin.  The adder provides the usual Sum and Carry outputs.  A D-type flip-flop IC11 (74xx74) allows any Carry out signal produced when the inputs are summed to be fed forward so that it can be included in the next bit addition.

Front Panel Display and User Controls

To make the computer more user fiendly and to facilitate development and testing, a serias of user displays have been added to allow the operation to be observed.

Output Register and Binary Display

The Sum output of the ALU is fed to a deserialiser shift register IC12 (74xx164).  This is a serial-in, parallel out shift register which drives an array of 8 LEDs.  This is a convenient means of monitoring the serial output from the ALU, and visualising it as an 8-bit number on the array of LEDs.

Hexadecimal Display

In addition to this simple binary output indicator, a further two shift -registers  IC13 and IC 14 are used to create a latched hexadecimal display of the last two serial output packets from the ALU. They are based around an 8-bit serial to parallel shift register (74xx595), which has the added advantage of having an output latch. This allows the output to be latched at the correct time to show the correct bit packet on the hexadecimal display. This latch signal needs to be timed using the /Y1 output of the bit-decoder IC2.  The first output byte is latched on IC13 and displayed, then after 8 clock cycles the packet has been transferred to IC14 and latched to the display. This allows the "last two" results of the ALU operation to be viewed.  Additional shift registers and hex displays could be added to extend this display if required.

Input Toggle Switches.

This is a series of 8 push buttons which allow a single byte to be entered into the machine. The push buttons are each connected to a D-type flip-flop IC16  (eg 2 x 74xx74 ) which allows a single push of the switch to toggle the state of the output.  The 8 signals are displayed  both on a binary LED display and a hex display - and are loaded into a parallel to serial shift register IC15 using a "Deposit" button.  This allows simple and accurate numerical entry.

Here's the latest update on my bit serial cpu project.

My design was getting too complicated and approaching 30 IC packages, so I took a step back to re-assess the design.

I eventually realised that most modern memory hardware is based on parallel buses - so I acknowledged @EdS advice and decided that a hybrid parallel-serial design is going to provide a minimum hardware solution - and probably best speed and hardware optimisation.

The architecture has evolved to a parallel input, a bit serial alu and a parallel output. It is vitally important to minimise the hardware needed for parallel to serial and serial to parallel conversion.

I decided to split the hardware design up into two distinct stages, with some goals to aim for.

Stage 1 is a prototype to fully characterise the bit serial ALU. I decided on a simple "Calculator" application with switches to enter the operands and the operator.

This can be implemented in about 15 standard TTL packages for an 8-bit design, or 19 packages for a 16-bit design. There is no memory interface, you have an input register and an output register - and very little else.

Stage 2 builds upon the lessons learnt from Stage 1. Speaking from experience, it takes a lot of gates to turn a shift register into a recirculating (permanent) register. It is best to switch to the parallel domain and use an octal register like a 74xx574 to hold your data.

Stage 2 adds a memory interface to the ALU, along with instruction decoding, control unit, branch control logic and a real stored program operation.

Stage 2 adds approximately 10 packages to the basic design - investigated in Stage 1. I have allowed for a 16-bit program counter (4 x 74xx161), a ROM, a RAM and some jump registers with conditional branching hardware.

As I progress with this project, I see an 8-bit cpu in about 25 packages and a 16-bit cpu in about 30 packages.

This represents a 50% discount from previous designs - so you can still have a 16-bit TTL cpu on a 4" x 4" board from JLC PCB. It might be slow - but it's gonna blast a 1976 6502 !

People will be rather anonyed if you harm a 6502 any way ,shape or form.

1976 reminded me about the Kenback 1 computer. http://www.kenbak-1.net/index.htm
I thought it was out around 1975-1976; but looking at the web page It came out in 1971-1972.
A serial computer, with very small memory and SSI logic. (14 pin dips).
A reproduction site is here. http://www.kenbakkit.com/index.html

Ben.

Another update on the bit serial cpu project.

I am still using H Neeman's "Digital" simulator - which is proving to be a useful design tool.

I took the rational decision of separating the ALU from the memory so that I could focus on each as a separate entity.

The ALU section boils down to around 15 very common TTL packages - which includes the clock and timing circuit, zero detection, instruction decode, and jump logic. The circuit includes some toggle switches so that you can toggle an operand in and single step through an operation, viewing the ALU results on a 7-segment hex display.

I did a rough pcb layout of this circuit, and in standard DIL TTL, it will fit onto a 100x50mm pcb - effectively the top half of a 100x100 cheap pcb from JLB PCB.

The memory sub-system has been based around an 8-bit wide RAM. But the instruction word is 16 bits, so I have to latch the upper byte and wait for the lower byte. This takes 16 clock cycles.

I have got the machine to run a simple stored program - essentially increment or decrement the accumulator and then jump on zero.

I have yet to sort out the memory Load and Store instructions - but these should be easier now that the cpu is executing code from memory.

The memory sub-system is 7 additional ICs - and this will create a demonstrable 8 bit machine in about 24 packages.

Stretching this to a full 16-bit machine with 16-bit address space can be done in fewer than 30 packages.

The 16-bit implementation would use 16-bit wide memory - and this would make system operation a bit easier, with very little implications on chip quantity or additional complexity.