Aeroplane and Commercial Aviation News - Volume 116 - Page 32
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Interavia - Volume 23 - Page 1088
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Scientific and Technical Aerospace Reports - Page 1300
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Scientific and Technical Aerospace Reports - Page 408
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Bulletin signalétique 890: Industries mécaniques génie civil. ...
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Jane's Weapon Systems - Page 1022
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Remington, Williams, Wright "An outline of the Ferranti data handling system proposed by the Sud-Aviation Group for project L.A.S.".
Proceedings of the 1968 International Colloquium on Aerospace Computers in Rockets and Spacecraft, published by the Centre National D'Etudes Spatiales, Paris.

The computer proposed was a small G.P., single address machine, operating in a serial-parallel mode. It had a word length of 13 bits. A short word length was desirable in order to minimise hardware, and it appeared that at least 12-bits were required to specify an efficient instruction code. The data word length used in associated scientific experiments was to be 13-bits, including parity, and so this word length was adopted for both instructions and data.
... The design was based on low-power T.T.L. logic. The central processor design used some 280 integrated circuit flat-packs, and was estimated to weigh 3 Kgms and have a power consumption of 5 watts. The speed of a basic instruction, using a 1 micro-second beat and an 8 micro second store cycle time, was about 36 micro-seconds. This was adequate to deal with the estimated computing load of 20,000 simple orders a second.

In the L.A.S. study the achievement of reliability and power consumption targets presented the greatest difficulty; the achievement of acceptable weights, costs and computational speed did not appear to be difficult.

Although the L.A.S. project was not funded, the study of a number of new aerospace and control projects, including jet-engine control and the ARINC 561 Inertial Navigator, indicated that there was a need for a small cheap and reliable computer with similar facilities to those of the L.A.S. machine, but with a higher computing power.

A minimum hardware solution and short word length were still acceptable and were desirable, not only to achieve high reliability, but also low cost.

The word length was reduced to the more conventional length of l2-bits, but the design included features to facilitate multi-length working. The required increased computing power was achieved by adopting fast T.T.L. logic (Ferranti Micronor 5), an existing fast (1 microsecond) core-store, a more powerful function code (including hardware division) and a parallel arithmetic unit. Simple orders are executed in about 4 microseconds and multiplication in 14 microseconds. The central processor unit comprises some 360 dual in-line elements and occupies 10 cms length of a JATR box.

The FM 1200 computer has been used as the basis of a number of studies of aircraft systems, including engine control in multi-engined aircraft and advanced military navigation and attack systems. In general in these systems, where the computing capacity of the machine has been approached, it has been advantageous to use multiple computer systems in order to provide reversion. These studies have also indicated that 24-bit Computations are adequate for navigation, and that there is not significant reduction in the proportion of double-length working should the machine word length be increased to 16-bits.

For a number of applications the FM 1200 is now being offered with semi-conductor memories.

An example of an advanced input/output system is the Ferranti 'S' Interface, which has been developed for use with the FM 1200. This enables the computer or the peripheral to initiate the transfer of single words or blocks of words from the computer store. The transfer takes place serially between the buffer register in the computer C.I.E. and the peripherals, the buffer register being loaded or unloaded from the store by a parallel-transfer Data Interrupt. At the termination of a sequence of transfers a Programme Interrupt can be initiated for the data to be serviced, but until this happens the transfer proceeds effectively independently of the computer. The rate of serial transfer over the peripheral-computer highway is dictated by the peripheral and can be at a peak rate of up to 8 megabits a second.

... the ARGUS 400, and we believe it to be the first micro-miniature airborne computer to be designed and developed in Europe. It is basically a re-engineered version of the earlier ARGUS general purpose computers, initially developed for the control of the BLOODHOUND missile. It is a 24-bit, "one and a half" address machine using a serial arithmetic unit and a ferrite-core memory operating in the parallel mode. The speed of the store is not fully used by the computer, and the resultant waiting time is utilised by allowing direct access to the store for input and output without loss of computing speed. The computer also has facilities for directly addressing input-output by program. Some applications of this computer will be described later, but it is of interest to note that its main airborne application has been in experimental navigation systems. This confirms our view that a 24-bit data word is sufficient for most navigational systems, and illustrates the flexibility of using a variable program store. In these applications protected volatile program storage appears to have been satisfactory.