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 Great British Microprocessors - the Viper (1985 to 1991) 
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1666
(In the tradition of celebrating technical success even when associated with commercial failure, and because Michael mentioned the machine and I already had some materials...)

32-bit micro from Royal Signals & Radar Establishment (RSRE), "Verifiable Integrated Processor for Enhanced Reliability" or VIPER
A fifth the complexity of its peers
And yet, "several million transistors" (Really?? Citation.)
Designed in HOL
Programmed in Newspeak

There's a machine description in Appendix 1 (page 19) of The VIPER Microprocessor (J Kershaw, November 1987) where we learn it just has A X Y and PC, all 32 bits, and a 20 bit address range - so 20 bit addresses fit in the one-word instructions.
It also has a single one-bit flag as the status register.
There's a hint that addition might be slower than a logic operation!

The doc tells us about simulating the device in Algol68 at 50 instructions per second on a VAX. And a microprogrammed emulator thingy by Gemini Systems Inc. running at 200,000 IPS. And that took only 168 instructions on the Gemini! Chip design is in ELLA (I think I might remember that from my Plessey days.)

The fangs of the VIPER (Nature, August 1991)
VIPER is the first commercially available microprocessor whose design is claimed to have been proven correct. The controversy provoked by the claim reveals fundamental disagreement about the meaning of 'proof'.
See also here, page 86.

At last, the guaranteed fault-free chip. New Scientist, 3 October 1985
PRODUCTION work should begin next week on the first 32-bit chip in the world with a design that has been proved mathematically to be correct. ... The RSRE's scientists have designed a new software language to work alongside the Viper chips. The language, called NewSpeak, does not allow a programmer to design a program that has errors in it ... And why is it called NewSpeak? It was designed in 1984.


But it ended badly:
Last month, a small computer consultancy in Worcester went the way of
many others in the current recession, and called in the liquidators.
But the closure of Charter Technologies is not just another hard-luck story:
it contains tough lessons for any company contemplating doing business with
the Ministry of Defence.
New Scientist 13 July 1991

More info here: Hardware Implementation, Processors and EMC (Prof. Chris Johnson, School of Computing Science, University of Glasgow)
and here:
Microprocessor Based Protection Systems Andrew Churchley (Ed.) 1991

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Wed Oct 12, 2016 6:30 am

Joined: Wed Apr 24, 2013 9:40 pm
Posts: 207
Location: Huntsville, AL

Thanks for the links. It does refresh some of the concepts I held regarding this particular device. It is interesting that it's register set appears to follow that of the 6502. It seems that there was an appreciation of the simplicity of the 6502 at both Royal Signals & Radar Establishment (RSRE) and Acorn.

Michael A.

Wed Oct 12, 2016 3:23 pm

Joined: Wed Apr 24, 2013 9:40 pm
Posts: 207
Location: Huntsville, AL

Found another specification document that is good to read in addition to the one provided by BigEd above: Formal Specification of the VIPER Microprocessor in HOL, C.H. Pygott.

Michael A.

Fri Oct 21, 2016 12:50 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1666
Revaldinho and I were looking through some Ferranti documents yesterday, and noticed a mention of VIPER (VIP 1) being implemented in a 6000 gate DS-series ULA (1.5u, 1987). Indeed it turns out this was a design goal, of sorts, with the initial implementation being by MEDL on the UK5000 array (5000 usable gates.) Here's some text from the a19461 pdf linked upthread:

Repetitive arrays of cells are much more amenable to CAD than random logic networks, leading to a more highly automated and probably more predictable design process. A custom chip starts from scratch in accumulating reliability statistics, whereas a chip based on a widely used standard substrate can benefit from the experience of other devices. VIPER has therefore been based from the start on gate array and cell array technology. The first VIPER implementation used the UK5000 gate array. This was a joint project between RSRE, Marconi Electronic Devices Ltd (MEDL), British Telecom, and a number of other UK electronics companies. "5000" refers to the number of "usable" gates on the device, allowing for the inevitably less than perfect efficiency of the layout process. The chip actually contains 410 dedicated single-bit latch circuits and 2400 general purpose gate cells, each made up of two N-channel and two P-channel MOSFET's. The latch cells are internally clocked, and are permanently connected together in a serial "scan path" register so that all of them are accessible for testing. The manufacturing technology of UK5000 is silicon gate CMOS, [2 microns]. Layout of a UK5000 chip is fully automatic, once a gate-level description exists. The CAD software is interfaced to the logic design language ELLA, so that a design can be taken automatically from a gate-level description in ELLA through to the final silicon.
VIPERS have been fabricated by MEDL on UK5000 substrates, and (as a private venture) using the CELLSOS Silicon-on-Sapphire process... A third implementation is in progress at Ferranti Electronics Ltd using their proprietary CDI (bipolar) process, which offers good environmental performance with reasonably low cost. All three families of VIPER chips are pin-compatible.The VIPER design is just practical on UK5000, with a bare minimum of "frills". Several highly desirable features have had to be left out of the prototype design... [multiplication, division, a bigger register set, support for redundant parallel VIPERs, DRAM support]

Wed Jul 17, 2019 9:43 pm
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