Started to play a around with magnetic media at the time (IBM 8" floppy,IBM 2310 disk drive) with ballpark numbers
for data.20 bits works nicely with GCR and seems the best fit for a simple fat table OS but I need to play with numbers
more.
LATER... the numbers say go 18 bits, with 2kb block sizes. 4kb per track for the 2310. 6kb for the floppy.(fudged).

Mother board is done, save for power supply caps.

most of the routing done, just some final cleanup. 6.25" x 5.75"
.75 uS cycle time. 1.5 uS memory access.

Slowed it down to emulate 1.8 uS memory cycle with 8Kb core as a ROM area, and mostek 4K drams for main memory.
The 1974 model has 48Kb for program and 16Kb for the OS buffers. 32Kb for the shell and file system program
in Small C. Disk is 192 tracks/2 heads and 4Kb per track using a 1.5K word FAT table and 1K block size. ~ 1.5 Mb
per disk. 2 platters reserved, A whopping 1200 baud serial I/O with a glass TTY.

Finished draft of the of the ALU and Memory/IO cards. 6.75" x 5.00".

Small C generates rather large code so I need more space than a better compiler would.
32K user space, 32K o/s space could be the base model then.

I hope to have layout checked on the weekend, and have the PCB's made up.
Soon I will have built a 18 bit computer, if it works that is another story.

CPLD's are nice you need 10/10 PCB rules and 56 mill pads to route the many leads
at 25 mill spacing. Of course KICAD does not have said footprints for DIPS/PLCC's and Passive Devices.

(8/8 rules at 20 mils give 2 tracks between pads.)

Now that all the routing is done, I am playing with the idea of a real time clock interrupt to the CPLD logic.
I will use what fits with CPLD, 15 Hz and 1 Hz

Could you use 60Hz from a power supply point?

Is this computer strictly virtual? How were the images generated?

All the power supplies no longer have a 60 hz power transformer.

The cpu is virtual under windows and dosbox-x.
Just the cross assembler and small c compiler exist for now
and the virtual machine.

The images are kicad of hardware pcb's. Working on the hardware
gives me a better idea of the virtual machine. I found a $50 cpld
programmer and am now able to use 128 cell CPLD's in my design.

Next week will be busy hardware wise, getting PCB's sent for production.

The alu and memory pcb's are out the door. Just waiting for the pcb service to review and bill me.
Reply: Too busy, sending to dentist for drilling. $2000.00
Both PCB's have been paid for about $100 Canadian for each set of 5 pcb's, and 24 hour service
and DHL shipping.
Customs is another $25 at the door.

The mother board passes the smoke test.
Power switch and reset work, as well as the de-bounce integrated circuit.
The leds have a built in dropping resistor and are really bright.
Too bright to photograph.

The photo looks amazingly like the KiCad artwork.

No dimmer pot on the board?

Kicad's 3d modeling is nice, but it can't help with passive parts that don't fit the footprints from the junk box.
Needed to modify all the common footprints from 62 thous to 56 thous pads so I can have fatter
power traces between pads, 22 mills and a 25 mill grid for traces and via's.

I may have the other PCB's delivered Saturday, next week will be testing hardware,
and programming the PAL's and CPLD's,

Other than specific chips like RAM,EEPROM,and IO, 74ls14, 22v10's,16v8's, AT1508's cover all
the chips I seem to need for now.

Major milestone hardware wise, the front panel seems to work.
Needed to revise the microcode encoding, and some pin out changes.
Register swap and exchange removed at this time.

Mostly microcode logic debugging today. I/O is simplified to just 1 UART @ 1200 baud.
Major milestone, the halt instruction works, as well as Run/Stop from RAM or ROM. IRQ untested.
Fixed immediate instructions to work properly.
Need to now get a bootstrap loader written,

> Major milestone hardware wise, the front panel seems to work.

Nice! Always good to see concrete progress!

The bootstrap loader is working now, and small test programs
are running from ram. EEproms are so nice here, just like core.

I have Compact Flash and Real time clock I/O card now to create a
schematic for. When this done I have all the planned i/o devices
I need.
The goal here is a paper tape setup,then later a full scaled machine
from the 70's.
Changed the memory card CPLD's now to write disable the bootstrap in
the EEPROMs. Now safe from any CODE Monkeys that show up at 3 am.