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Tridora-CPU - an FPGA stack machine CPU for Pascal
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oldben
Joined: Mon Oct 07, 2019 2:41 am Posts: 885
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The CMOS version of the PDP 8 had a stack. IF I was redesigning the 8 , I would have 002X as auto decrement resisters that map to 001x and Jump to subroutine pushes the PC using 17 as the stack.
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| Wed May 28, 2025 2:04 am |
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slederer
Joined: Sun Oct 20, 2024 9:43 pm Posts: 11
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oldben wrote: The CMOS version of the PDP 8 had a stack. IF I was redesigning the 8 , I would have 002X as auto decrement resisters that map to 001x and Jump to subroutine pushes the PC using 17 as the stack. Ah, didn't know that, interesting. Come to think of it, the PDP-8 had quite a long lifespan if you count the microprocessor versions and considering the (for the 1970s) limited architecture.
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| Wed May 28, 2025 10:57 pm |
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slederer
Joined: Sun Oct 20, 2024 9:43 pm Posts: 11
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Another update for the Tridora-CPU - it now has a data cache in addition to the instruction cache. This has a noticable impact on compile times: building "hello,world" now takes 15 seconds instead of 20. As with the instruction cache, it just caches the 16 bytes that the DRAM controller always delivers. Since with the stack machine architecture you often read, write and read the same location again, it was important to implement it as a write-back cache. Otherwise the cache would be invalidated too often. Thankfully, the write-back mechanism was not as complicated as I feared. I have updated the benchmark results at https://gitlab.com/slederer/Tridora-CPU/-/blob/main/examples/benchmarks.results.text. If you compare the performance when running code from DRAM without any caches to the current version, you get a three times better performance in the empty loop benchmark. In comparison to running without data cache but with instruction cache, you get 1.6 times better performance. The other big thing is this update is the audio controller. I finally hooked up the Digilent AMP2 PMOD and added something like the sound generator chips of the early 1980s to the logic design: Four channels of rectangle waves and a noise generator. Then I thought, that is boring, and reworked it so that now it can to interrupt-driven sample playback at (at least) 32KHz (mono). Here is a video where you can hear the Tridora-CPU making noises and playing music: https://youtu.be/p3USZ40Du24And now I guess it is already time to plan this year's christmas demo...
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| Mon Oct 13, 2025 10:05 pm |
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BigEd
Joined: Wed Jan 09, 2013 6:54 pm Posts: 1864
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Thanks for the update - good to see small caches making good performance improvements!
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| Tue Oct 14, 2025 10:06 am |
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mmruzek
Joined: Sun Dec 19, 2021 1:36 pm Posts: 107 Location: Michigan USA
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Thank you for the link to your video. I enjoyed watching it. The sound quality is really amazing! Michael
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| Tue Oct 14, 2025 11:28 pm |
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e2k
Joined: Mon Nov 28, 2022 2:51 pm Posts: 10
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Very nicely done! And even a lot of documentation, impressive! Looking forward to the Christmas Demo 
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| Sat Dec 06, 2025 12:19 pm |
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e2k
Joined: Mon Nov 28, 2022 2:51 pm Posts: 10
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BTW: a porting guide would be nice  Just a brief one, half a page describing what is important, like: you use switches (what for, reset is obvious, but ..) LEDs really needed, what do they show VGA out, using 12 bit ./hysnc/vsync ... Audio? PWM, 2 channels etc. Was just looking at it, and looking for a board which is close to a digilent artix7 ... But seriously, great job!
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| Sat Dec 06, 2025 3:03 pm |
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e2k
Joined: Mon Nov 28, 2022 2:51 pm Posts: 10
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BTW, I don't think(?) it would be too difficult to make a a100t version for the digilent boards. The 35/50/75/100 are pretty similar, so just a changing the chip and start a new P&R ... shouldn't be more than that ...
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| Sat Dec 06, 2025 8:16 pm |
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slederer
Joined: Sun Oct 20, 2024 9:43 pm Posts: 11
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Yes, there should always be more documentation  As you mentioned, maybe a short description about how the PMODs are wired up would be nice, also the clock routing and BRAM usage. I also wanted to do a diagram for a long time that shows what happens in the CPU at the different sequencer stages and how they overlap. For example, the instruction fetch (first stage) is started in the last stage of the previous instruction. I'm not really using the buttons and switches by the way, that they are declared in the Verilog sources is a leftover from earlier debugging. I probably should clean that up sometime... If you want to port this to another board, I'd be happy to help, just ask away! The closest board would be the Arty-A7-100T. For that you would probably have to adjust some of the pins in the constraints file and you're done. The next best (and cheaper) thing would be the Arty-S7-50T (Spartan-7 instead of Artix-7 parts). The Arty-S7-25T is at an even lower price, but it does not have enough BRAM to get 128KB of video memory + 64KB SRAM out of it. You could try to reduce the SRAM to 32KB, that will slow things down but should work.
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| Wed Dec 10, 2025 10:35 pm |
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e2k
Joined: Mon Nov 28, 2022 2:51 pm Posts: 10
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I have one of the QMTech boards with an artix7-200 on it, also DDR3, but on anther bank ... have PS/2 mouse & keybord, DVI, PWM audio, SD-Card interfaces If you would remove all the buttons, LEDs etc. from the top file, would be nice  Tough to check, if they are not used somewhere after all ... One of those Christmas projects 
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| Thu Dec 11, 2025 10:05 am |
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slederer
Joined: Sun Oct 20, 2024 9:43 pm Posts: 11
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Sounds like a great board, the 200T has lots of BRAM resources. You could make 1MB of SRAM and leave out the DRAM controller. That should be enough for most of the existing software.
Is that the QMTech Wukong board? That seems to have a 50MHz clock crystal (Arty has 100MHz), so you would need to adjust the settings for the MMCMs in cpuclk.v and display_clock.v accordingly.
You might be able to change the VGA output to DVI output with not much of a hassle. There are several open source digital video output implementations in Verilog. Easier of course would be to get the VGA PMOD (uses two adjacent PMOD connectors) if you want to use a VGA monitor.
I hope I can find the time this weekend to clean up the top file. Although you might want to keep one or two leds as they can be useful to determine if a program has crashed. For example, the third led lights up whenever a BRANCH instruction is executed, so it will light up brightly if the CPU runs in an endless loop.
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| Sat Dec 13, 2025 12:39 am |
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e2k
Joined: Mon Nov 28, 2022 2:51 pm Posts: 10
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No, I got one of the "core Boards", and made my own carrier for it, so I have all of it on the same board (DVI, serial via USB, PS/2 mouse & keyboard, audio as PWM, ...) DVI is working, we have it in other projects. Using the SERDES2 of the artix, we can go up to HD ... Look forward to see the clean-up, Christmas is coming 
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| Sat Dec 13, 2025 1:22 am |
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slederer
Joined: Sun Oct 20, 2024 9:43 pm Posts: 11
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I have done a little bit of clean-up now. Unused inputs for top are gone. The leds are still there, because I use them  Also managed to get rid of some warnings for unconnected ports, although there are still many left, for example, when 32 bits of address lines are declared but the module uses only 31 of them. I have no good solution for that yet, luckily in Verilog that just works, I have heard that in SystemVerilog, that is an error.
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| Mon Dec 15, 2025 12:02 am |
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e2k
Joined: Mon Nov 28, 2022 2:51 pm Posts: 10
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LEDs are OK, buttons are worst. In case there is some hiddedn waiting for a button press in the code, and one is debugging it for hours  LEDs which I don't have, I just get to unused pins, and it should be OK. THANKS again,
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| Mon Dec 15, 2025 12:54 pm |
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