Sid wrote:
A TTL CPU with core memory sounds awesome, do you have any PDF's of the circuit and block diagram we could have a look at ?
Sid
Sorry by it is just emulation, of core for timing. if core stacks were around it would be easy to interface as it is designed
around the read/write back memory cycle.
The best example may be the PDP-8 /E schematics.
They use a 20 MHZ clock to generate core timing logic. strobe here, pulse there, latch now.