good idea. minus 0 as the reset fault.
Can you tag the internal registers for address and data, where a zero in address is a fault or null pointer?

I made the registers a byte wider so that tags or flags could be added to them, but this is not implemented. There is a bit reserved to indicate a pointer in a register. It could be combined with the value to indicate a fault.

The MSI interrupt controller was outputting an NMI all the time. This occurred because a state of no interrupts was indicated with the same code as an NMI (with one more top bit set).

Pretty much decided to drop predicates and the PRED modifier from the ISA. It turns out to be tricky to implement with multiple threads present. I think I got it implemented but sheesh. Predicates are adding a fair bit of logic to the design. It is a bit disproportionate to the value. There could be multiple active predicates in the pipeline for each thread and everything needs to be tracked.
A predicate fault occurred during testing. The fault occurs when the commit pointer is sitting at an instruction waiting for a predicate and there are no longer any active predicates. It is a hardware issue. I decided not to spend time debugging.

The design may clock faster without the predicates. Branches automatically predicate instructions anyway if they are in a short branch shadow.

For some reason the exception flag on the ROB entry was being set during enqueue. This caused all instructions to exception. It was supposed to be set only if there was a decode exception.

Spent about an hour figuring out why the reset jump was jumping to $FFFFC000 instead of $FFFF8000 like it should. Looked at the assembler encoding, instruction decoding, etc. Then I remembered that the memory file used to load the ROM was still pointing to the file for 2025. I switched this to the 2026 version to fix things.

Milestone:
The core is jumping to the reset address, so it is executing the first jump instruction after a reset now. And it is loading up instructions in the pipeline. Still more work to do…

Bug Fixes
There was no valid signal associated with an I$ miss address. This led to cache lines for the default miss address to be fetched repeatedly. This would affect performance, which was obvious on the sim trace as long spaces between instructions. A valid miss address signal was added to rectify this.

Micro-ops were not marked as valid when translated resulting in all micro-ops being treated as NOP operations. No instructions were executing except branches performed in the extract stage. (Branches in the extract stage operate on raw instructions not micro-ops).

It seems that NOPs are not always indicated as such in the decode bus. I am not sure where the issue is. But since they are normally marked done right away and do not get dispatched, lacking a NOP indicator causes the machine to hang. Just wondering if to add dispatch logic for this case. Eventually, I figured this one out.

A couple of the test conditions for instruction dispatchability were incorrect. This meant instructions would not dispatch causing the machine to hang. Dispatchability conditions are pre-computed before they are used.

Fixed up the use of the old 'instruction' structure to the newer micro-op structure in a few places. Some of the older code was ported that did not use micro-ops. I should really go through all the code and ensure there are no references to the old structure.

The super-fast, super compact instruction dispatcher from the other day did not work. It required a fix, not sure how timing is impacted.

Choosing the ready RSE (reservation station entry) written as a function was re-written as a module. It did not work as a function, always returning -1 meaning no RSE was selected.

I found a better way to handle flow control dependencies. All instructions are marked as depending on the stream they are associated with. It only matters for instructions that have dependencies like stores for instance. When the state of the stream resolves to a known value, then the instructions for that stream are unmarked as dependent. I think this is more efficient than the previous mechanism that searched backwards through the ROB for flow control dependencies. To do this a stream state array had to be added along with some state management.

A case statement in the LSQ (load store queue) was coded incorrectly. I must have been drunk at the time.

Results do not seem to be written to the register file. I found one or two bugs related to this but have not found the panacea yet. There are so many bugs it is hard to know where to start.