Last visit was: Fri Jul 19, 2024 5:33 am
It is currently Fri Jul 19, 2024 5:33 am



 [ 55 posts ]  Go to page Previous  1, 2, 3, 4  Next
 Simple Large Computers 
Author Message

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
I got the logic for the front panel done. The mc14490 hex bounce eliminator and a tl7759 power supervisor meets my needs for the front panel switches and reset.Clock gen still neds work.


Sun Jun 11, 2023 8:42 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1789
Looks to me like 0.156 inch is 4mm - so that is metric! But in any case, I'd be surprised if any modern PCB package didn't offer both metric and inches.

Front panel is a nice thing to have, but very much a construction project.


Mon Jun 12, 2023 6:42 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
I have my clock generator logic done. 3 speeds ahead and one back for reverse polish :).
The pre scaler will divide by 3 or 2 or test of 1. Test selects a push button rather than the nomal
osc. Idle is a 3 phase clock, with Req Mem a 5 phase clock. a =< 0 for adress will generate .NOT.
VMA and give a Idle cycle.
Front panel state logic is the last PAL for me to do. Then I can start drawing schematics.
Ben.


Wed Jun 14, 2023 3:52 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Timing was just to complex. The clock now uses a 5 mhz osc, and has 3 or 4 cycles.
.6 us for idle. .8 us for memory ref. Some front panel timing moved here.
The front panel pal is now done. All the pins on the card edge connectors have been
assigned. 74LS540's are used as generic inverters as they have slight schmitt trigger
in them. Ben.


Wed Jun 14, 2023 7:24 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Now using 6.144 MHZ clock as I can get those. 200 ns memory @ 4 cycles. Wait state for IO or slow memory.
Idle 3 cycles. LS logic in a few places. Good for the IBM XT era.
Ben.


Sun Jun 18, 2023 1:10 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Moving to 5.5 Mhz for 250 ns memory in the xt era.
1973 - 1978 74181 TTL logic 2 us core memory -- ibm 1130 sized
1978- 1983 2901 bit slice PDP 11 rack sized
1983- 1988 2901 s100 computer size ** this one planned
1988+ 2901 cmos ibm pc sized, ?? 200 ns ram


Sun Jun 18, 2023 10:39 pm

Joined: Sun Mar 27, 2022 12:11 am
Posts: 41
The HP PA-RISC TS1 from the mid 1980s ran at 8Mhz. It used F series TTL and was built around the '181 with some PALs, and 25ns SRAM. It used a 3 stage pipeline, had a cache, virtual memory, floating point, and could support up to 128MB of RAM.


Mon Jun 19, 2023 12:16 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
They also a had people better skilled than myself, in PCB layout , mechanical design
and board stuffing. Using F componts, really impoves timing in critical spots.

I need to go back to the drawing board for timing, may add a tubo button.
First I need to get it working in LS parts, then high speed. Using CMOS 2901's,22v10's,74ACT823,74ACT821 parts for low power rather than speed.
Ben.
PS. Yes that is how it worked,
Turbo off 7.1 Mhz 14.18 Mhz /2
Turbo on 4.77 Mhz 14.18 Mhz /3


Mon Jun 19, 2023 6:25 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
I have gone to a 8 mhz clock, to give a 500 ns short cycle and 750 ns long cycle.
I get a about .5 mips with this setup, average. I need to design the memory cards first, then the alu.
2 cards 18 bits wide will be used for memory (low and high) to keep the wiring simple.
The internal 2901 cycle is about 280 ns ballpark, using 20 ns 22v10's.
I don't think I will use a MMU but relocate stuff from a base register for now.
Ben.
PS. 8 mhz needs 150 nS ram/rom and 12 Mhz needs 100 nS ram/rom.
PPS: 12 Mhz needs faster PAL's for 240 ns internal cycle.


Mon Jun 19, 2023 6:08 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Playing the numbers game, a 9 mhz clock works best for me.
Have to split 18 mhz by 2 for that. A short cycle is .33 uS and a long one .66 uS.
This way a can get a 1 MIPS rating with slow memory.
12 Mhz also works nice, .25 uS and .5 uS, but I only have 5 ns margin.
(1.33 MPS)
Ben.


Wed Jun 21, 2023 5:39 am

Joined: Sat Feb 02, 2013 9:40 am
Posts: 2104
Location: Canada
Reminds me of the 8.1818 MHz dot clock of the C64. The timing works out well for a composite display in that case. It was used with slow memory. 300ns DRAMs I think.

How do you arrive at 0.33us and 0.66 us given an 18 MHz (55ns) clock?

_________________
Robert Finch http://www.finitron.ca


Thu Jun 22, 2023 7:14 am WWW

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
robfinch wrote:
Reminds me of the 8.1818 MHz dot clock of the C64. The timing works out well for a composite display in that case. It was used with slow memory. 300ns DRAMs I think.

How do you arrive at 0.33us and 0.66 us given an 18 MHz (55ns) clock?

18 mhz / 2 is 111 ns.
The clock is divided by 3 for two phase clock.
Address strobe and clock, 333 nS.
For a memory request wait states are added as needed,
in this case 3. 666 ns total for a memory cycle.
Faster versions will add 1 wait state for RAM, 2 for ROM
and 4 for I/O.

For the first test version the mother board will use a 8 mhz clock .
This gives me .375 and .750 us, similar timing to a 4 mhz z80.

The wide data path, 36 bits lets me have +- 21 bit offset for immedate
constants and addressing modes, thus most instructions are one or
two memory cycles long.


Thu Jun 22, 2023 7:48 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Ben's 1973 computer MSI TTL and Surplus 36 bit Core
Code:
   JUNE 23 2023 byte version
   36 bit CPU SUMMER 73 mos timing
   Core emulation
   1.2 us (7.4 mhz) or 1.5 us surplus core (6 mhz)
   ac/pc display switch
   load,examine,deposit,run/stop

    9    8    7    6    5    1    3    2    1
  +----+----+----+----+----+----+----+----+----+
  |COOO:AAAA:XXXX:MA+#:####:####:####:####:####|
  +----+----+----+----+----+----+----+----+----+
                     1 111XX 0X RAM 10 ROM 11 IO
 
                OP      CC       
     0 #  A     ST/STB  -       
    1 S  B     XOR     Z                 
    2 U  C     OR      S
    3 V  D     AND     Z+S     
    4 W  E     LD/LB   !C   
    5 X  F     CAD/CAC !(C+Z)
     6 Y  G     SUB/SBC T
     7 Z  H     ADD/ADC T
   
    LEA/MEM%/MEM#/SFT/CTL   1.2 1.5 uS
    MEM-X/MEM-A             2.4 3.0 uS
    JMP-X/JMP-A/JSR         2.4 3.0 uS
    SCC                     1.8 2.0 uS
    BCC/DCC                 2.0 2.5 uS



Using 22v10's and cmos parts , I have 30 chips for the CPU card.
The rough schematic on paper is done. The mother board is the next
design to start on. Bus termination will be here.
The only real trickey part will be memory as I need to use byte wide through
the hole memory chips for the 9 bit wide rom and ram as I can program them.
Ben.
PS: MRAM does look nice for a real core memory. I wish they had that in 1973.


Fri Jun 23, 2023 8:23 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Spent most of the day looking for parts on ebay. Ordered 30 CY74FCT823ATPC 's
instead of 74ACT823's as none could be found as dip 24.


Fri Jun 23, 2023 8:33 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Ordered the 50 pin male and female bus connectors, off ebay. Hopefully they will be matching and the correct size. Ben.


Wed Jun 28, 2023 6:49 pm
 [ 55 posts ]  Go to page Previous  1, 2, 3, 4  Next

Who is online

Users browsing this forum: CCBot and 0 guests


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Jump to:  
Powered by phpBB® Forum Software © phpBB Group
Designed by ST Software