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 Getting it working. 
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Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Now a hashed out memory, i/o card - 32K x 24 ROM/RAM, 6850 ACIA and 32MB compact flash.
Total memory space 128K 24 bit words. Exact decoding needs to finalized, after I get the
CTL card in the door, and working.
Ben.


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Wed Jan 10, 2024 4:35 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
I got the CTL card in and doing single step debugging with a logic probe. Found logic errors in 3 Pals so far.
Hope to have the front panel working soon.


Mon Jan 15, 2024 7:26 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
The front panel is now working. No memory reads FFFFFF. Now just to wait for the memory card to arrive.
I wonder if I can get no mem to read BADBAD. :)


Tue Jan 16, 2024 6:31 am

Joined: Sat Feb 02, 2013 9:40 am
Posts: 2104
Location: Canada
Quote:
I wonder if I can get no mem to read BADBAD. :)

You could use some XOR gates or inverters to flip bits to get BADBAD.

_________________
Robert Finch http://www.finitron.ca


Tue Jan 16, 2024 6:48 am WWW

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
robfinch wrote:
Quote:
I wonder if I can get no mem to read BADBAD. :)

You could use some XOR gates or inverters to flip bits to get BADBAD.


I might use 'BADADD' as a ROM padding constant or a NULL POINTER.


Tue Jan 16, 2024 8:44 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Well early this morning I got the front panel working with 28c256 eeproms as memory.
I can't get it to run programs yet, like HLT.


Fri Jan 26, 2024 11:38 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Had a zombie computer. Bad solder joint -- some times living, some times undead.
Forgot to add READ on a instruction fetch with the micro code. Soldering up a real IO card
for more testing.


Fri Jan 26, 2024 8:34 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Found still more unconnected solder joints. Mis labeled switches on the memory selection. Wrong pal for the alu module location.
Skips, shifts and JSR neededs to tested. Run/stop logic has strange behavor, 1st instruction ignored on run. unfixable.
About 50% working. Only 64K of memory space.


Sun Jan 28, 2024 2:45 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Another day, another VW err BUG. LOAD operation was adding, not loading.
Finding a good DOS to study is hard to find, most computers 18 bits or less
were paper tape systems, too small to have a DOS. 24 bits never made it into
the 70's that I can find. ICL 1900 and George 3 for later study.


Mon Jan 29, 2024 9:39 am

Joined: Sat Feb 02, 2013 9:40 am
Posts: 2104
Location: Canada
Quote:
Finding a good DOS to study is hard to find,
There is always MS-DOS. The sources for early versions are on the web now.
There are a couple of other OS's like MINIX.
There is Commodore DOS too.
And OS9.

Were you looking for a mini-computer OS? Or is a micro-OS okay?

I found source code to implement file system functions written in C on the web a while ago, but I cannot seem to find it on my workstation. It is out there somewhere.
Were you looking for assembler code or is C okay?

_________________
Robert Finch http://www.finitron.ca


Tue Jan 30, 2024 6:09 am WWW

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
I am looking for older stuff simply because I have huge amount fast core memory - 24K words @ 2.2 us. Well for 1969 :)
24 bits is a small computer in the UK and 16 bits for the US and 18? trits for the USSR for a computer that could have a DOS
rather than paper tape I/O like the PDP 8.
I have 32K of rom space, that I can put in device drivers and system functions and even some bios code.
I better make JMP # to BRANCH # so my code is more relocatable.
I just want a few good examples with out getting bogged down with details, and real OS with interrupts.
I need to keep it simple because it a pain to reinsert the eeprom chips after every programming.


Tue Jan 30, 2024 11:04 am

Joined: Sun Oct 14, 2018 5:05 pm
Posts: 62
oldben wrote:
I am looking for older stuff simply because I have huge amount fast core memory - 24K words @ 2.2 us. Well for 1969 :)
24 bits is a small computer in the UK and 16 bits for the US and 18? trits for the USSR for a computer that could have a DOS
rather than paper tape I/O like the PDP 8.
I have 32K of rom space, that I can put in device drivers and system functions and even some bios code.
I better make JMP # to BRANCH # so my code is more relocatable.
I just want a few good examples with out getting bogged down with details, and real OS with interrupts.
I need to keep it simple because it a pain to reinsert the eeprom chips after every programming.


The PDP-8 has a disk operating system - it's called OS/8.

In the UK: The Elliot series computers mid to late 60s are run from tape though.

Also, UK, You may want to lookup the OS6 operating system for the Modular One computer. Written in BCPL Multi user, but one user at a tine. It was part of the inspiration for my own BCPL OS for my Ruby 816 project.

This:

https://retrocomputingforum.com/t/os6-a ... -1972/1907

Has many links to it.

As for the 8-bitters needing tape... Try telling that to the CP/M people, or Northstar DOS or any of the disk opersting system on the 8-bitters of the late 70s - Apple II, PET, TRS-80, etc. ...

Your eeprom issue is easily solved - you replace most of the eeproms with RAM and leave a little monitor that can download code into the RAM via serial and run it from there, or arrange the eeproms to be in-sutu programmable as I did with my 6507 system and the WDC 65c134sxb system and many others - e.g. ATmega/Arduino UNO, etc.

Cheers,

-Gordon


Tue Jan 30, 2024 12:52 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
The PDP 8 needs 12K for OS/8, not the standard 4K PDP 8 with a TTY.
As for the 8 bit cpu's 32kb memory and floppy was big money over the 8K basic in ROM
and cassete.


Tue Jan 30, 2024 7:48 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Uart testing for tommow, as I write basic io routines @ 1200 baud.


Thu Feb 01, 2024 10:33 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
I tried to take a short cut with bus timing, and that idea did not work. I needed to change the ' -wait ' line for sigle stepping
to ' memory bus is ready ', for gating the tristate buffers for data transfer. I also changed the write data timing. This seems
to make the ACIA happy as I can read/write to it now. Single clock stepping is dropped.


Sat Feb 03, 2024 6:02 am
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