I'm building an 8-bit CPU out of 74HC logic in KiCad — seven module boards, no
backplane, everything daisy-chained on three ribbon cables. This is the clock
module, the first board of the set and the one that has to be trustworthy
before anything else can be debugged.

Available for sale https://www.tindie.com/products/spartatux/clock-module-dip/

**Two logic packages, 22 parts total.**

- **74HC4060** — crystal oscillator and 14-stage ripple divider in one package.
16 MHz HC-49 across pins 11/10, 1 MΩ feedback resistor across the same pins,
27 pF at the inverter input, 100 pF at the far end behind a 2.2 kΩ series
drive resistor.
- **74HC14** — hex Schmitt inverter. One gate buffers the raw 16 MHz off the
oscillator node, two form the step debounce and the output driver, one drove
the inverted output, and the two spares have their inputs tied to ground.

Everything else is passive: five caps, six resistors, an LED, three switches,
two headers.

## Eleven taps, selected with a jumper wire

An 11-pin header carries every available frequency and a single pin beside it
is the selected one. You pick the clock rate by moving a jumper.

| Tap | Divisor | Frequency |
|---|---|---|
| `OSC16M` (via HC14) | ÷1 | 16.000 MHz |
| `Q4` | ÷16 | 1.000 MHz |
| `Q5` | ÷32 | 500.0 kHz |
| `Q6` | ÷64 | 250.0 kHz |
| `Q7` | ÷128 | 125.0 kHz |
| `Q8` | ÷256 | 62.50 kHz |
| `Q9` | ÷512 | 31.25 kHz |
| `Q10` | ÷1024 | 15.63 kHz |
| *(Q11 not brought out by the '4060)* | | |
| `Q12` | ÷4096 | 3.906 kHz |
| `Q13` | ÷8192 | 1.953 kHz |
| `Q14` | ÷16384 | 976.5 Hz |

The frequencies are silkscreened beside the header so the board documents
itself on the bench. The 16 MHz tap comes off the oscillator node through a
Schmitt inverter, not through a divider stage.

## Or stop it and press a button

A slide switch picks between the jumpered tap and a manual step pulse. Step is
a pushbutton pulling a 10 k-pulled-up node down, 100 nF across it, into a
Schmitt inverter — about a millisecond of RC, then a hard edge. The switch
common carries a 10 k pull-down so the output stays defined while the slider is
between contacts. A second button pulls the divider's reset high, which zeroes
every stage at once — useful when you want the same phase relationship twice
while probing.

Welcome!

Thank you.

I posted a video where I tested the module: https://youtu.be/9UTUwAtBXAQ?si=aIjak4U4F7wqB6Aa

I intente to build a full 8-bits CPU,
My intention was to finance my project with the sale of this module, but I am not very good at sale.
But I am still going to build it, but just slower.

Hi Spartatux,

I look forward to following your progress.

A clock module is a good place to start. A ripple counter will produce clock outputs that may not be in phase with each other. This only matters if one is trying to drive logic using two different clocks that have some fixed relationship. Another option may be to use a synchronous counter.

Clocks can get very complex. 16 MHz is a decent choice for a base frequency. If one is considering video at some point, other frequencies (25MHz VGA), 14.31818 MHz NTSC, may be desirable.

I am reminded of the clock module that was offered at one time by BurchEd I think based on the ICS525. It uses an internal PLL and has ports that can be connected to DIP switches for setting the divisors. It is capable of high frequency operation and works at 3.3 or 5V.

It may be desirable to include a real-time clock at some point, eg DS1307? It might also go in the empty space on the board. There are existing modules in the marketplace for RTCs however.

Clocks are pretty application specific and the higher frequency stuff is typically on-board where it will be used, not in a separate module, to limit issues with signal integrity.

Thank you for your advices. I will try to integrate some of them in my next version.
I also thought that a very slow clock could be useful for debugging

So this is my v1.2, I changed the power and the clock out connectors for Molex connectors.
I added a 4040 so it as now slower tap for CPU debug.

The goal of the clock module is to run and debug the CPU. If an other module needs a clock frequency, I will make clock for that module.

I planed to divide the CPU by modules, and the ALU by cards.