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The next design - a octal 20 bit cpu
http://anycpu.org/forum/viewtopic.php?f=23&t=1112
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Author:  oldben [ Thu Apr 04, 2024 7:32 am ]
Post subject:  The next design - a octal 20 bit cpu

Going back to more 1968 style computer. Word addressing. Accumulator design rather a register to register design.
Subroutine calls on even bountry, and single word 19 bit addressing. This way I can use CALL theading for threaded code. 8 registers including
the PC.
More inspection of the new oder code, conficts with some other decoding,thus I am back to two word calls and the orignal order code.

Author:  oldben [ Thu Apr 11, 2024 6:09 am ]
Post subject:  Re: The next design - a octal 20 bit cpu

Moving clock generation to the ALU card as well. The ALU gets to use the master clock first.
Moving up to 1984, with a 1.5 uS memory cycle time -- ram . A 1977 version 1.8 uS core or ram.
PS: Looking at the chips I have, I may tweek it for 150 ns ram, and add a wait state for IO.

Author:  oldben [ Sun Apr 28, 2024 5:42 am ]
Post subject:  Re: The next design - a octal 20 bit cpu

Gone back to a hex format.
The schematics are roughed out, but no layout is done yet. This will be a emulated design with stubbed IO
routines, for the next few months. Getting close to a "hello world" type test program.
PS: Last minute addition - signed bytes (10 bits).

Author:  oldben [ Mon Apr 29, 2024 5:55 am ]
Post subject:  Re: The next design - a octal 20 bit cpu

Changed from Big Endian to Little Endian, so I can read and write disk blocks on the PC and port over to Compact Flash
later. Disk IO would be a modified IBM patter drive from 203 tracks to 225 tracks. 4Kb per track like the PDP-8, 10 bit bytes, GCR. Some sort of strange fat system.
Now I need a name for this beast, and time for software.

Author:  oldben [ Sat May 11, 2024 8:47 pm ]
Post subject:  Re: The next design - a octal 20 bit cpu

I have the emulator printing "Hello world".
I got dosbox-x running and cross compiling small c version 1.2.
I need to write a simple FAT file system ( 8 inch floppy 10 bits/byte GCR single sided)
and the small C libs. System setup 462 Kb per floppy, two floppies per system. 48K ram + ROM BIOS
+ 2 serial at 1200 baud?
about 1976.

Author:  oldben [ Sun May 19, 2024 10:32 pm ]
Post subject:  Re: The next design - a octal 20 bit cpu- NOT

I have improved the design, since I could only find 18 bits, in the bit bucket.
This is a serial design, 3 bit nibble. The only rare parts are a 13 mhz osc,
CY7C122 (256 x 4 ) 25 ns ram and a 74H74.

2.5 uS memory cycle time.
Operate 2.5 uS
auto 5.0 uS
index 7.5 uS
The emulator will print "hello world", but more testing needs to be done.
Ben.

Author:  256 [ Fri May 24, 2024 2:05 pm ]
Post subject:  Re: The next design - a octal 20 bit cpu- NOT

oldben wrote:
3 bit nibble

I've never heard of a n[yi]bble being anything other than 4 bits.

Author:  oldben [ Sat May 25, 2024 5:17 pm ]
Post subject:  Re: The next design - a octal 20 bit cpu- NOT

256 wrote:
oldben wrote:
3 bit nibble

I've never heard of a n[yi]bble being anything other than 4 bits.

Next you will tell me a byte is 8 bits.
Other notes.
The design of the serial 18 bit cpu is on hold, just too slow, and floating point
is still too small.
The order code of my 20 cpu will be revised from what I learned on the 18
bit machine, with 31,1,8 float.
Ben.
PS: Evil laugh, bytes are now 10 bits, and nibbles half that.

Author:  BigEd [ Mon May 27, 2024 5:36 am ]
Post subject:  Re: The next design - a octal 20 bit cpu

(Welcome, 256! It does seem unconventional for a nibble not to be 4 bits, but as Ben notes, sometimes a byte isn't 8 bits, certainly on this forum where any CPU architecture decision is open for experimentation...)

Author:  oldben [ Wed May 29, 2024 12:46 am ]
Post subject:  Re: The next design - a octal 20 bit cpu

Code:
draft #1

 The ben 20 is a medium speed digital computer using LS TTL parts with a
a word width of 20 bits and a byte with of 10 bits. 9 digit binary floating
point.4K dynamic ram or 1.8 uS core memory provide the base 48Kb of memory
with 32kb ram and ROM/CORE for bootstrap and other operating system
routines.
Emulation of the CPU, will use later PAL and bitslice parts.

Cpu model:

The cpu has a Carry flag and 4 general purpose registers A,B,C,D and 3
index registers S X Y and instruction pointer Z (zero).
Index registers do not affect the carry.

Adressing modes are register indirect:
            +r -r r% r+ r-
indexed:    r n
immediate:  # n

opcode postfix  .   byte
                %   register

Instruction format:

  modes:
  0     nop and shift

        nop
     5    4    3    2    1   
  +----+----+----+----+----+
  |0000| AAA|  0 |    :    |
  +----+----+----+----+----+

        shift ac

     5    4    3    2    1   
  +----+----+----+----+----+
  |SSSS| AAA|  0 |    :    | NORMAL
  +----+----+----+----+----+

  1     set condition
        if ac condtion is true set ac to constant
        else set false (0)

     5    4    3    2    1   
  +----+----+----+----+----+
  |NCCC| AAA|  1 |    :+###|
  +----+----+----+----+----+

 2     memory ref reg indirect
    (EFA)= AAA  (STORE)
    AAA  = AAA OP (EFA)
 

     5    4    3    2    1   
  +----+----+----+----+----+
  |COOO|PAAA|  2 |BXXX:+###|
  +----+----+----+----+----+
    P PRE ADDITION
    B BYTE

 3     memory ref INDEXED
    (EFA)= AAA  (STORE)
    AAA  = AAA OP (EFA)
 
     5    4    3    2    1   
  +----+----+----+----+----+
  |COOO| AAA|  3 |BXXX|    |
  +----+----+----+----+----+
  |####|####|####|####|####|
  +----+----+----+----+----+
   
 4    jump to subroutine
      memory ref BYTE imediate

      JSR register indirect
      T = (efa)
      (--S)= Z,Z=T
 
     5    4    3    2    1   
  +----+----+----+----+----+
  |0000|PAAA|  4 | XXX|+###|
  +----+----+----+----+----+
    P PRE ADDITION

    memory ref BYTE imediate
    AAA = AAA OP #
     5    4    3    2    1   
  +----+----+----+----+----+
  |COOO| AAA|  4 |+###|####|
  +----+----+----+----+----+
   
   
 5   lea and control
     lea
 
     5    4    3    2    1   
  +----+----+----+----+----+
  |0000| AAA|  5 | XXX|    |
  +----+----+----+----+----+
  |####|####|####|####|####|
  +----+----+----+----+----+
    control
     5    4    3    2    1   
  +----+----+----+----+----+
  |ffff|    |  5 |    |    |
  +----+----+----+----+----+

     5    4    3    2    1   
  +----+----+----+----+----+
  |0001|    |  5 |    |    |  HALT
  +----+----+----+----+----+

 6   jump on condition
     register indirect
 
     5    4    3    2    1   
  +----+----+----+----+----+
  |NCCC|PAAA|  6 | XXX|+###|
  +----+----+----+----+----+

     
 7   jump and register operate
     jmp indexed
 
     5    4    3    2    1   
  +----+----+----+----+----+
  |0000| AAA|  7 | XXX|    |
  +----+----+----+----+----+
  |####|####|####|####|####|
  +----+----+----+----+----+
   
     reg operate
     AAA = AAA OP XXX

     5    4    3    2    1   
  +----+----+----+----+----+
  |COOO| AAA|  7 | XXX|    |
  +----+----+----+----+----+
 
OPCODE TABLES:
     REGISTER

          AAA   XXX       
     0    A     A         
     1    B     B
     2    C     C
     3    D     D
     4    S     S
     5    X     X
     6    Y     Y
     7    Z(PC) Z(ZERO) OR #

     MEMORY REF

     OOO  OP       
     0    ST    (EFA) = AAA           
     1    ADD/C  AAA  = AAA +  (EFA) + ?0,C
     2    SUB/C  AAA  = AAA + ~(EFA) + ?1,C
     3    CAD/C  AAA  = ~AAA + (EFA) + ?1,C
     4    LD     AAA  = (EFA)
     5    OR     AAA  = AAA |  (EFA)
     6    AND    AAA  = AAA &  (EFA)
     7    XOR    AAA  = AAA ^  (EFA)

    SHIFT
    LATER
   
    LOGIC CC
    LATER




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