Last visit was: Fri Jul 19, 2024 5:04 am
It is currently Fri Jul 19, 2024 5:04 am



 [ 9 posts ] 
 Ben's 16 bit computer 
Author Message

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
I have compacted the 20 bit cpu, to 16 bits.
MMU's are a PTA, but you need split code and data, user and system.

Code:
    draft  JUNE 16 2024

16 BIT segmented CPU.
64Kb user data space, stack
64Kb user program space
64Kb sys  data space, sys stack
64kb sys  program space

Cpu:
The cpu has a Carry flag and 7 general purpose registers and PC/Z
special registers.  ADX is addition that does not affect the carry flag.
ADD/SUB/CAD and shifts affect the carry.

Adressing modes are register indirect:
      INDEXED   r + #
      AUTO (A)  -r r% r+

opcode postfix  .   byte
                ,   unsigned byte
                %   register
           

Instruction format:
 +-+---+---+---+---+---+
 |Q|OOO|AAA|C+#|###|###|  0 # QUICK 7 BITS
 +-+---+---+---+---+---+
 
 +-+---+---+---+---+---+
 |Q|OOO|AAA|CMM|XXX|?RR|  1  MEMORY REF
 +-+---+---+---+---+---+
 
 
OPCODE TABLES:
     REGISTER

          AX  RR        MODE
     Q = 0
                        CTL,QUICK #
     Q = 1   
     0    A   DIRECT    JMP/JSR,SCC/JCC   
     1    B   -R        LEA/HLT,REG OP,SHIFT
     2    C   R%        OP BYTE ? SIGNED,UNSIGNED
     3    D   R+        OP WORD ? USER SPACE,SYS SPACE
     4    S   
     5    X           
     6    Y             
     7    Z/P
 
     MEMORY REF

     OOO  OP   C     
     0    ST/STP      (EFA) = AAA
                      (EFA) = AAA PROGRAM SPACE
           
     1    ADD/ADC  AAA  = AAA +  (EFA) + ?0,C
     2    SUB/SBC  AAA  = AAA + ~(EFA) + ?1,C
     3    CAD/CAC  AAA  = ~AAA + (EFA) + ?1,C
     4    LD/      AAA  = (EFA)
            LDP    AAA  = (EFA) PROGRAM SPACE
   
     5    OR/      AAA  = AAA | (EFA)
             EQV   AAA  = AAA XNOR (EFA)
     6    AND      AAA  = AAA &  (EFA)
             XOR   AAA  = AAA ^  (EFA)
     7    ADX      AAA  = AAA +  (EFA)
             ATX   AAA  = AAA +  (EFA)<<1

     micro code 256 x 24
     87 654 321
     RA:SMM:CCC
     01:1PP:CCC PANEL
     00:100:CCC DI-EI/QUICK #
     1a:smm:CCC NORMAL DECODE 


This will be virtual machine for now, but a real cpu seems possible, once I get the micro code
defined.
One option is to have the carry flag select byte high,low
and make atx ac = ac + (efa)>>1 setting carry. This will break C,
how ever, but gives you 2x the data/code space.


Sun Jun 16, 2024 8:19 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Code:
draft  JUNE 18 2024

16 BIT segmented CPU.
version #1 no segments

Cpu:
The cpu has a Carry flag and 7 general purpose registers and PC/Z
special registers.  ADX is addition that does not affect the carry flag.
ADD/SUB/CAD and shifts affect the carry.

Adressing modes are register indirect:
      INDEXED   r + #
      AUTO (A)  -r r% r+
 
   CPU 16
  +----+----+----+----+
  |OOOO:1AAA|?XXX:MMRR| MEMORY
  +----+----+----+----+
  |OOOO:0AAA|+###|####| BYTE #/NOP
  +----+----+----+----+
 
opcode postfix  .   byte
                ,   unsigned byte
                %   register
           

Instruction format:
        ST      OP
0   A   LEA     OP REG           
1   B   JSR -R  JCC -R   
2   C   JSR R%  JCC R%
3   D   JSR R+  JCC R+
4   S   -       SFT
5   X   CTL     SCC #-1
6   Y   CTL     -
7   Z/# CTL     SCC # 1
8       ST R)   OP R)   WORD
9       ST -R   OP -R   WORD
A       ST R%   OP R%   WORD
B       ST R+   OP R+   WORD   
C       ST R)   OP R)   BYTE ?=UNSIGNED
D       ST -R   OP -R   BYTE ?=UNSIGNED
E       ST R%   OP R%   BYTE ?=UNSIGNED
F       ST R+   OP R+   BYTE ?=UNSIGNED
QUICK   NOP     OP #    -128+127

     MEMORY REF

     OOO  OP   C     
     0    ST/STP      (EFA) = AAA
                      (EFA) = AAA PROGRAM SPACE
           
     1    ADD/ADC  AAA  = AAA +  (EFA) + ?0,C
     2    SUB/SBC  AAA  = AAA + ~(EFA) + ?1,C
     3    CAD/CAC  AAA  = ~AAA + (EFA) + ?1,C
     4    LD/      AAA  = (EFA)
            LDP    AAA  = (EFA) PROGRAM SPACE
   
     5    OR/      AAA  = AAA | (EFA)
             EQV   AAA  = AAA XNOR (EFA)
     6    AND      AAA  = AAA &  (EFA)
             XOR   AAA  = AAA ^  (EFA)
     7    ADX      AAA  = AAA +  (EFA)
             ATX   AAA  = AAA +  (EFA)<<1

     micro code 256 x 24
     87 654 321
     RS:MMA:CCC
     01:PP0:CCC PANEL
     01:001:CCC NOP,TRAP/QUICK #
     1S:MMA:CCC NORMAL DECODE 



Small C seems to compile. Off to find a bigger C


Wed Jun 19, 2024 4:32 am

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1789
> Small C seems to compile

A milestone! Congratulations!


Wed Jun 19, 2024 7:08 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
I now have the simple segmented version working, and small c outputting code (64kb) and (64kb) data segment.
Planned software: Fat table disk format,sub directories,single user. 1977 ish hardware time frame. 16Kb for the OS and 32Kb for user space.
Next month to work on the hardware version.


Mon Jul 01, 2024 4:59 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Picked up a 68000 SBC, and plan to emulate a 32 bit cpu with18 bit addressing.


Fri Jul 12, 2024 8:01 am

Joined: Sat Feb 02, 2013 9:40 am
Posts: 2104
Location: Canada
Which SBC?

_________________
Robert Finch http://www.finitron.ca


Fri Jul 12, 2024 4:49 pm WWW

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
robfinch wrote:
Which SBC?

The one now sent by Snail Mail. :)
https://www.tindie.com/products/rosco/r ... -full-kit/
(You save by having no case, or floppies)


Fri Jul 12, 2024 6:05 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Code:
draft  JULY 12 2024

32 BIT segmented CPU.
version #1 no segments 512 Kb address space.

Cpu:
The cpu has a Carry flag and 8 general purpose registers and PC/Z
special registers.  (A,B,C,D) ADD/SUB/CAD and shifts affect the carry.

Adressing modes are register indirect:
      INDEXED   r + # SHORT
      DIRECT    # ADR
      AUTO      r% r+
      PSH       -r

   CPU 32
  +----+----+----+----+
  |OOOO:UAAA|JSSI:xXXX| MEMORY
  +----+----+----+----+

 
opcode postfix  .   byte
                ,   unsigned
                %   register
index
    0xxx r%
    1xxx r+
    0xxx r] ####
    1nnn Z  ####         
    ±nnn QK
    ±nnn BR ####

Instruction format:
        ST      OP      JMP
0   A   CTL     QUICK   SCC           
1   B   LEA     REG     BCC
2   C   B R+    B R+    SFT #X
3   D/# B R]    B R]    BSR
4   W   W R+    W R+    JMP R+
4   X   W R]    W R]    JMP R]
4   Y   L R+    L R+    JSR R+
4   S   L R]    W R]    JSR R]

     OOO  OP   C     
     0    ST/PSH         
     1    ADD/ADC  AAA  = AAA +  (EFA) + ?0,C
     2    SUB/SBC  AAA  = AAA + ~(EFA) + ?1,C
     3    CAD/CAC  AAA  = ~AAA + (EFA) + ?1,C
     4    LD       AAA  = (EFA)
     5    OR       AAA  = AAA |  (EFA)           
     6    AND      AAA  = AAA &  (EFA)
     7    XOR      AAA  = AAA ^  (EFA)




Fri Jul 12, 2024 9:22 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Code:
draft  JULY 13 2024

32 BIT segmented CPU.
version #2 still no segments, 512Kb

Cpu:
Since this is planed to be emulated on 68000
endian is what ever the 68000 is.
A quick and dirty C emulator is planned.
The cpu has a Carry flag and 8 general purpose registers and PC/Z
special registers. 
ADD/SUB/CAD and shifts affect the carry.

Adressing modes are register indirect:
      INDEXED   r + # SHORT
      DIRECT    # ADR
      AUTO      -r r+
     

   CPU 32
  +----+----+----+----+
  |OOOO:-AAA|JSSI:IXXX| MEMORY
  +----+----+----+----+
  - reserved
opcode postfix
    .R   REG
    .Q   QUICK
    .B   byte
    .W   word
    .L   long
   

    II
    0   R+ or #
    1   -R
    2   Z]
    3   R]     
    SS
    0   OTHER
    1   .B
    2   .W
    3   .L
    J   JUMP
    0   OPS
    1   SHIFT and CONTROL

index
             low
    0xxx r+  XXXX high
    1xxx -r  XXXX
    1xxx r]  XXXX ####
    0nnn Z   XXX# ####         
    ±nnn QK  XXX#
    ±nnn BR  XXX# ####   

Instruction format:
        ST      OP      JMP
0   A   CTL     QUICK   SCC           
1   B   LEA     REG     BCC
2   C   B R+    B R+    SFT #X
3   D/# B R]    B R]    BSR
4   W   W R+    W R+    JMP R+
4   X   W R]    W R]    JMP R]
4   Y   L R+    L R+    JSR R+
4   S   L R]    W R]    JSR R]

     OOO  OP   C     
     0    ST         
     1    ADD/ADC  AAA  = AAA +  (EFA) + ?0,C
     2    SUB/SBC  AAA  = AAA + ~(EFA) + ?1,C
     3    CAD/CAC  AAA  = ~AAA + (EFA) + ?1,C
     4    LD       AAA  = (EFA)
     5    OR       AAA  = AAA |  (EFA)           
     6    AND      AAA  = AAA &  (EFA)
     7    XOR      AAA  = AAA ^  (EFA)




Sat Jul 13, 2024 10:42 pm
 [ 9 posts ] 

Who is online

Users browsing this forum: Bytespider, CCBot, DotBot and 1 guest


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Jump to:  
Powered by phpBB® Forum Software © phpBB Group
Designed by ST Software