MY hardware for a 9/18/36 bit computer keeps crashing. I need to build whole new system with proper buffering.
Design of a smaller 16/32 bit computer is planned first in emulation then later as hardware.7 registers plus pc,
.
this is 18 instruction types. No irq at the moment.

RISC-V 32E should be "easy". 16 x 32-bit registers. Probably do it in about 38 instructions.

Look at the Univac project... Or write an emulator for your existing N-bit system...

-Gordon

I refuse to go with RISC architecture, for hardware.
A micro RISC controller chip,how ever might make a good platform for custom CPU chip design in a
84 pin PLCC package? So would a small FPGA.
For now a simple emulator will suffice, but I have to revise the BIOS I have for the new hardware.
The BBC micro with a ARM CPU is close to what I want, as vintage hardware design,
(can it run in CANADA).
The instruction set, makes for simple code generation from a simple high level language, so this I will not change.
PS: tweeked the instruction set to have a short addressing mode off the frame pointer.

OK.



I'm sure there are several. So you'd write the code to emulate your retro CPU on the microcontroller, or implement it in the FPGA?
I presume you need many pins to give you a "classic" address and data bus...




Maybe you're not familiar with the PiTubeDirect project?

But you know about the BBC Micro - it was intended to be the IO processor for a 2nd CPU connected via the Tube. This is a high speed (for the day; 2Mhz) bus to exchange data to/from the 2nd processor - e.g. a faster 6502, Z80, 80186, INS32016...

PiTubeDirect Takes a Raspberry Pi and interfaces it to the BBC Micros Tube interface then has emulation software for every 2nd processor ever made, and many more. e.g. PDP11. Also, there is a framework that lets you write your own CPU, so you could use this to write your own CPU code (in C or ARM assembler) to test and run your own CPU, using the Beebs base unit to give you a handy keyboard/screen and filing system...

Then you can put your cpu into TTL/FPGA/whatever.

BBC Micros run perfectly well in Canada. Some have PSUs where you can switch the voltage - video output may be trickier. I have several here, but I'm in the UK.



But you need then then write that compiler - or work out how to adapt an existing one... The former is where I stalled on my
projects, but the latter was easy.

-Gordon

I am stalled on a self hosting FILE SYSTEM. The old chicken and egg problem.With the emulation I can fake a file system.
until I get one written.

I keep making changes. in the hardware for easy but dumb code generation.
Reverse polish is nice idea, but too complex for me. I have a short form word addressing mode off the stack pointer
that will let me access a local stack frame.

Since I was planning to use 3 words ( 16 bits) for floating I have 32 and 48 parameters,
a bit messy. I revised the micro code to use 8,16,48 bit data. The CPLD's for the design seem to build OK
so I will move onto getting the emulator working. I dropped the frame pointer as It needed negative offsets.

A retro filing system is not hard - but it depends on the features you want to implement.

Lookup "first fit" (and maybe "best fit") memory allocators and use that on a disk. It's not robust but it's very usable (also relatively fast) as it's just a big linked list of pointers to the next file. You need to guard against writing past the end of a file and you need to pre-create a file with a maximum size. After that, just read and write... You can use the first disk sector as the catalog - filename, offset of start of data and maximum size allowed will keep it simple to strt with and you can write the "compact"/"defrag" command later.



Evaluating RPN is easy - it's a stream of tokens, push a number, etc. do an operation. Repeat until out of tokens. lookup the Shunting Yard algorithm for an easy to use method of turning 1+2 into 1 2 + (It's how I do it in my Basic interpreter)

-Gordon

Expression parsing is left to right, with parenthesis changing priority. No boolean logic in expressions yet If added logic is -1 or 0.
No floating point. No unary minus.
Signed byte constants, but bytes are unsigned. Int data types 16 bit signed. Word data types (long) are 32 bits signed, Floating point 3 words. 31 bit mantissa, 15 bit exponent.
Clock timing needs to be changed from divide by 8 to divide by 10 for a needed internal wait state.
First trial timing is 2.5 uS for a memory cycle. Reserved a order code for a Excess 3 Addition.
Both the NOVA and the PDP 11 came out late 1969,So Thought I could use chips from that Era how ever I need to use 74163s
but I can only find them in a 1971 TI data book thus this is the release date of the CPU.
Ballpark timing looks ok, but no margin with the register file data path.
With PROM's coming out about 1975, timing for that version is planned to be 1.8 uS memory cycle.

The basic design idea, was with fast 16x4 ram and a ALU with lookahead one could run 1 16 bit ALU twice for 32 bit math in one slow (core) memory cycle. This is harder than expected with slow TTL logic in 1969. Random logic has 1250 nS alu cycle and
~1973 a 900 nS memory cycle ( some SSI 74SXX parts ) for BALL park timing with PROMS.
Now using 0200 (half word) page size for short form addressing ( page zero or local page ).Page zero is 0x200.(half words).
Code starts a 0x200.

Still too complex for register operations as I need a input multiplexer on both input registers.
Now I write the data to the io bus, and read it in.
Lea is now just loading a 17 bit address constant. Char constants unsigned.