As announced and discussed over on the 6502 forum, but surely of interest:
(Might be best to discuss over there)
Similar size and complexity, mostly better performance and code density compared to 6502. Well worth reading
the doc!
It's a 16 bit mini-RISC with an 8 bit bus, 16 bit instructions, 16 bit byte-addressable space, and 16 bit program counter, one flag bit.
It's presented as a verilog chip design for Tiny Tapeout. Assembler and emulator in python.
Code comparison for 8 routines
here.
Quote:
Well, after much vibe codery, Claude and I have managed to get a design ready for Tiny Tapeout!
https://github.com/mysterymath/riscyv02You can see a cool 3d view of the die here:
https://mysterymath.github.io/riscyv02Highlights:
- 8x 16-bit general-purpose registers (vs 3x 8-bit on 6502)
- 2-stage pipeline (Fetch/Execute) with speculative fetch
- 61 fixed 16-bit instructions
- 2-cycle interrupt entry (vs 7 on 6502)
- 1.0-2.6x faster than 6502 across common routines
- 13,280 SRAM-adjusted transistors (vs 13,176 for 6502 on same process)
Manual
here [in the repo]
