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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 961
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Time for a new thread. This is a 16/32 bit computer from the 70's as retro design.
The concept here is that core memory is 1/2 the speed of the ALU MSI chips from
the 74XX line. A 16 bit ALU can be double pumped to emulate a 32 bit alu.
1971 had the drop in logic prices for this idea to be possible, using state code
decoding. The goal here is 1.75 uS core memory cycle time. 1974 proms and 74Sxx came
out so a microcode version would be a1.33 uS or a 1.25 uS core memory cycle. Ball park timing
was done and looks ok for the TTL logic if built.
Now that the PCB's are being shipped, I can work on the programmable logic now.
A 74H74 is on reorder as I can't find one in my junk box.A 11.289 MHz oscillator is on
order from china, for the 1.75 core memory emulation.All the parts have been ordered
so it is just building it now using what I have in the junk box. Once working I the can try the correct speeds
when the parts come in.
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| Sat Aug 01, 2026 4:31 pm |
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Martin_H
Joined: Wed Jul 22, 2026 6:07 pm
Posts: 24
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You mentioned emulating core memory. That technology was before my time, so I don't know what that would entail.
I know reads were destructive and required a write back cycle. But I always assumed there was a memory controller, and the main CPU was shielded from those details.
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| Sun Aug 02, 2026 6:47 pm |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 961
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Martin_H wrote: You mentioned emulating core memory. That technology was before my time, so I don't know what that would entail.
I know reads were destructive and required a write back cycle. But I always assumed there was a memory controller, and the main CPU was shielded from those details. It was more the case in small machines, the CPU was built around the memory interface. In my case is generating a memory cycle is in two stages. a) load mar -- write back or refresh memory. b) read/write memory. repeat as often as needed. Keeping to this cycle one emulates core memory nicely but still able to use modern memory. The harder part is finding a crystal oscillator that is thru the hole and five volts. I can find a Gazillion 10 Mhz oscillators but not 13.3 Mhz oscillator for love or money. All the oscillator circuits are good only to 10Mhz so a 13.3 Mhz crystal is of little use. 1.5 uS core memory here. 16.6 Mhz needed for 1.2 uS core.
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| Sun Aug 02, 2026 9:07 pm |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 961
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oldben wrote: Martin_H wrote: You mentioned emulating core memory. That technology was before my time, so I don't know what that would entail.
I know reads were destructive and required a write back cycle. But I always assumed there was a memory controller, and the main CPU was shielded from those details. It was more the case in small machines, the CPU was built around the memory interface. In my case is generating a memory cycle is in two stages. a) load mar -- write back or refresh memory. b) read/write memory. repeat as often as needed. Keeping to this cycle one emulates core memory nicely but still able to use modern memory. The harder part is finding a crystal oscillator that is thru the hole and five volts. I can find a Gazillion 10 Mhz oscillators but not 13.3 Mhz oscillator for love or money. All the oscillator circuits are good only to 10Mhz so a 13.3 Mhz crystal is of little use. 1.5 uS core memory here. 16.6 Mhz needed for 1.2 uS core. Got the machine to operate the front panel. Looking at the clocks on the scope, I need to go slower than I expected. Right now 2.6 uS memory cycle.The memory card will be in soon, so I have to work on the software.
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| Wed Aug 05, 2026 12:54 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 961
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The power seems to glitch after the clock so I am adding .01 uF bypass caps. I ran out of caps, so I have more on order.
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| Fri Aug 07, 2026 4:39 pm |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 961
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Having problems with a faster clock, I am simplifying the logic for a 1970-1* year release, and 2.2 uS memory cycle
to compete with the IBM 1130. No interrupts at this time.
Ben.
* Can I help it if my Round Too Its are a tad slow.
PS. Simpler logic may permit a 9.21 MHz clock and 1.75 us cycle time. The 74LS74 is in the critical path
for timing, so I may need a 74H74. 74F74 is TOO fast.
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| Sat Aug 08, 2026 4:27 pm |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 961
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Rebuilding a clean ALU card with different by pass caps when they come in. .022 uF and 1 uF.
A 2.0 uS memory cycle about late 1971 if the 1.75 uS memory does not work. A fake 1.5 uS memory cycle 1974. For now just getting the proto-type card to work.
PS. Memory seems to work now, with test program. *Cpu halted at $0002*
Now on to I/O and bootstrap.
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| Mon Aug 10, 2026 5:30 pm |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 961
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Parts came in. Rebuilding the I/O card today and tomorrow the CPU card.
Thinking of skipping development if it works, and going to a 24/48 bit CPU.
PS. Finished the cards this evening. Short 2 bypass caps that I hand to fudge a
value for. Power supply glitch 1/2 the value compared to the original caps.
Tomorrow I plan to test the serial IO. Too dark, to dig around for cables tonight.
PPS. Need to revise memory timing again. 2.25 uS memory cycle time?
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| Thu Aug 13, 2026 5:39 pm |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 961
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Major Milestone. Bootstrap loader loads my halt test program and it ran.
$200
LD A #1
HLT A
END
Now on to testing what speed I can run at. I have a 74ALS74 on order and more bypass caps.
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| Fri Aug 14, 2026 7:40 pm |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 961
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Revised the order code, to have many of the features I omitted.This version omits irq service and indirect operations.
More control lines needed to and from the alu that I need to wire in for a alternate extended order code that may added. Added the FORTH
next instruction (untested).
About 93 macro cells for the ALU.
Current work is to revise the basic bios for the SD card (standard size) after I make a backup.
1.75 uS timing.
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| Sun Aug 16, 2026 1:40 pm |
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Martin_H
Joined: Wed Jul 22, 2026 6:07 pm
Posts: 24
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Thanks for keeping us updated on your progress.
What's the instruction set for this machine like? It sounds like a load/store accumulator machine. It also sounds like there's a hidden memory access register (MAR).
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| Tue Aug 18, 2026 1:54 pm |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 961
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Martin_H wrote: Thanks for keeping us updated on your progress.
What's the instruction set for this machine like? It sounds like a load/store accumulator machine. It also sounds like there's a hidden memory access register (MAR). *BACK TO THE DRAWING BOARD* The design is to have 32 bit alu as 16 bit alu in a low phase and then high phase on one clock cycle. The high pass is not working. I am putting this version on hold and just doing a 16 bit register machine,using only 16 bit instructions of the order code, for a smaller 16 bit machine that is able to run the cold start bootstrap.Once memory and I/O is debugged then I can think about debugging the 32 bit system again. The 32 bit machine is too complex to test at the moment. The IBM 1130 is the computing model I am using as a base, but with more modern ideas like immediate and stack operations. .
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| Tue Aug 18, 2026 4:15 pm |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 961
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oldben wrote: Martin_H wrote: Thanks for keeping us updated on your progress.
What's the instruction set for this machine like? It sounds like a load/store accumulator machine. It also sounds like there's a hidden memory access register (MAR). *BACK TO THE DRAWING BOARD* The design is to have 32 bit alu as 16 bit alu in a low phase and then high phase on one clock cycle. The high pass is not working. I am putting this version on hold and just doing a 16 bit register machine,using only 16 bit instructions of the order code, for a smaller 16 bit machine that is able to run the cold start bootstrap.Once memory and I/O is debugged then I can think about debugging the 32 bit system again. The 32 bit machine is too complex to test at the moment. The IBM 1130 is the computing model I am using as a base, but with more modern ideas like immediate and stack operations. . Had a nasty bug with a pin out on a CPLD, it did not match the schematic. A off by 1 on a label. A revise of the pin out solved my shift right problem. I have few more changes with logic on the schematic and I am done. ( wire in a few connections). I don't think I will play with this design for too long, add a mmu or go to 20 bits as the next project. It will be working 16 bit computer most likely tomorrow.
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| Thu Aug 20, 2026 5:28 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 961
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Simplified the chip logic pinout so the next CPU version (20 bits) will have a better layout. m=mode a=ac x=index # constant c=condition sense o=opp jcc jmp on condition scc set on condition Code:
AUGUST 20 2026 CPU 72
LAST OF THE ROOM FILLING COMPUTERS
_____##########_____ CLK
##########__________ ECLK
ALU FUNCTIONS AC CC SHIFT
# OPCODE FUNC
0 ST STORE z 0 -
1 ADD ADD x z 0
2 SUB SUB y s C
3 ADC ADC s s+z S
4 AND AND a ~c
5 OR OR b ~c+z
6 EQV EQV c true
7 LD LD d true
inactive bus FFFF
16 bits
6543 2109 8765 4321
+----+----+----+----+
|MOOO:MAAA|MXXX|C###| normal
+-------------------+
|0OOO:0AAA|####|####| quick
+-------------------+
RS:MMM:CCC micro code
ST OP
0 CTL/HLT QUICK PAN
1 DSP QUICK PAN
2 JSR JCC PAN
3 LEA SCC PAN
----------------------------------
4 R+
PSH REG
5 [R]#
6 , INDIRECT R+
SFT
7 , INDIRECT [R]#
% reg operand
. char (quick)
, indirect
----------------------------------------------------------------------
future 20 bit cpu
0987 6543 2109 8765 4321
+----+----+----+----+----+
|.MMM|COOO:AAAA|XXXX|####| normal
+------------------------+
|0000|COOO:AAAA|####|####| quick immediate
+------------------------+
Now to wait for a rainy day to back up to poor man's cloud. 
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| Thu Aug 20, 2026 10:23 pm |
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