I built a nonlinear FPGA computing core with persistent internal state and a 343-node 7×7×7 topology.

This is Gen1. Later generations already exist, but Gen1 is the one I am opening for public inspection.

It does not follow a conventional CPU pipeline model, so I am especially interested in feedback from people who build their own CPUs, soft-cores, and FPGA architectures.

Source, RTL, tests, and documentation:
https://github.com/etoyruben-wq/R-CORE-

A patent application has been filed for the architecture.

Run it. Break it. Change the topology. Port it. Show me where it fails.

I am not looking for “interesting”.

Show me tests.