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 [ 8 posts ] 
 Remote-debugging and bus-cycle tracing a 68000 over USB 
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Joined: Fri Jun 20, 2014 5:25 pm
Posts: 4
Location: London, UK
Some of you may be interested in this project which I finished a couple of months ago:

http://hackaday.io/project/1507-USB-MegaDrive-DevKit
https://www.youtube.com/watch?v=mEH7a-a8dvQ
https://www.youtube.com/watch?v=JxBzxhMhANI
https://www.youtube.com/watch?v=dLoudQc8L08

It's a 100% open-source (hardware & software) FPGA/SDRAM-based USB development cartridge for the Sega MegaDrive, an old 68000-based game console, but the techniques I use are potentially applicable to other 68000 systems (& potentially other CPUs too). The MegaDrive worked by just mapping cartridges containing mask ROMs directly into the 68000's address-space, so that's what my cartridge emulates. You could modify it to connect to a bare 68000 with very few changes.

The features that are relevant here are:
  • The ability to have the 68000 boot from the same SPI flash as the FPGA by having a small (84 bytes) bootstrap PROM built into the FPGA, which loads a 2nd-stage bootloader from SPI-flash.
  • The SDRAM-controller is fast enough to interleave access by the 68000 and the host, making it effectively dual-port, with no wait-states on the 68000 side.
  • The ability to proxy GDB over USB & do source-level debugging on the target: set breakpoints, single-step, examine and update registers and memory, etc.
  • The ability to nonintrusively stream a trace-log of every bus-cycle executed by the target (with a 20ns timestamp) over USB and written direct-to-disk: with a 2TB drive you could trace all day!

The whole thing was designed to be constructed at home with only a decent soldering iron (and a little skill & patience) required.

The cartridge is made from two PCBs connected together:
  • A completely general-purpose 4-layer Xilinx Spartan-6 LX9 board with 16MiB SDRAM, 512KiB flash, a fast (~42MiB/s) USB interface, an SD-card slot, 46 well-grounded FPGA I/Os and 8 USB-accessible I/Os, with a component cost for 10x of about USD 30.
  • A MegaDrive-specific 2-layer "bridge" board with three 5V->3.3V level shifters (one bidirectional, for the data bus), with a component cost for 10x of about USD 10.

Unfortunately I don't have any to sell, but I do have some spare PCBs that I might be willing to sell at cost (about $7.56 for the FPGA board and about $3.68 for the bridge-board) provided you can assure me you have the tools & experience to solder the 0.5mm-pitch chips!

Chris


Fri Jun 20, 2014 5:55 pm WWW

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1807
Welcome Chris, thanks for the interesting post! And thanks for open-sourcing your project, that's always appreciated.

Cheers
Ed


Fri Jun 20, 2014 7:02 pm
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Joined: Fri Jan 10, 2014 9:46 pm
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Sun Jan 11, 2015 12:39 pm
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Joined: Fri Jun 20, 2014 5:25 pm
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Location: London, UK
legacy wrote:
you have a great solution for a faster data connect, i very appreciate it!

Thanks, legacy!

In a very real sense this is just an example project for demonstrating the capabilities of FPGALink (which is what provides the fast USB data connect you mention). It's used by hundreds of people worldwide in many corners of industry and academia, mainly for high-speed data acquisition and instrumentation. It's even used on a fleet of satellites in Earth-orbit!

Anyway, good luck with your RISC project (is this a RISC softcore using your own ISA? if so I'd love to hear more about it...), and I hope you find my stuff useful.

Chris


Sun Jan 11, 2015 12:59 pm WWW
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Sun Jan 11, 2015 1:36 pm
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legacy wrote:
unfortunately i will never have the time and the resources to...add the machine layer to any existing C compiler

I had a similar project idea a few years ago but didn't get much further than laying out the ISA encodings and implementing it in software simulation. I spent a couple of weeks digging in the GCC codebase, and got to the point where adding a new ISA to GAS was working clunkily, along with a build of GDB capable of doing source-level debug of assembly-language code using a remote-serial connection to the simulator (unfortunately this was before I started publishing everything [warts and all] to GitHub so I don't know where that code is, or even if I still have it). However, the GCC back-end itself is rather complex, especially the optimizer's pattern-matching rules. I suspect it may be easier to build a Clang/LLVM (rather than GCC) back-end, but I have an ideological preference for licences with a strong copyleft clause like the GPL.

Chris


Sun Jan 11, 2015 2:41 pm WWW
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Wed Jan 14, 2015 3:42 pm
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Joined: Fri Jun 20, 2014 5:25 pm
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legacy wrote:
which ISA have you designed ? which processor does it look similar to ?

Sorry, I missed this question. The ISA was my own. I basically wanted a fixed 32-bit instruction word-length and simple decoding logic. In practice it's a mish-mash of ideas from MIPS and SPARC with some ideological influence from 68000. The main aim was to learn about the GCC back-end by implementing a back-end and optimizer for a completely new architecture. But that job turned out to be harder than I expected, and the project sort of fell by the wayside. I'm easily distracted by shiny things, unfortunately.


Wed Jan 28, 2015 10:43 am WWW
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