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 Thor Core / FT64 
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Joined: Wed Nov 20, 2019 12:56 pm
Posts: 86
robfinch wrote:
The Thor2022 scheduler component is driving me crazy. It is now reporting as being over 100,000 LUTs in size, totally ridiculous and blowing the LUT budget, when included in the top module. If I synthesize the module by itself, it reports as being 51 LUTs in size, which I think is the proper size. So, I am experimenting to try and find out why the difference.


That smells like a RAM block not being inferred - if it works in isolation, does the full integrated design maybe end up doing something like feeding the output of one memory block directly into the address input of another?


Fri Aug 26, 2022 9:15 am

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1795
Location: Canada
Quote:
That smells like a RAM block not being inferred - if it works in isolation, does the full integrated design maybe end up doing something like feeding the output of one memory block directly into the address input of another?
It does work like that a little bit. One 8x3bits wide ram is used to address a second ram. I figured it may make an 8x8 matrix but that is only about 3200 LUTs. I had a very complex scheduler and it worked out to about 20,000 LUTs in size. I figured it may be turning the RAM access into a matrix. So I went ahead and really simplified the scheduler and things went nuts. I am sure it is just something that I cannot see ATM.

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Robert Finch http://www.finitron.ca


Sat Aug 27, 2022 3:53 am WWW

Joined: Wed Nov 20, 2019 12:56 pm
Posts: 86
robfinch wrote:
It does work like that a little bit. One 8x3bits wide ram is used to address a second ram.


I'm going to hand-wave here, since I'm fuzzy on the details (and they no-doubt vary between FPGAs anyway), but my guess would be that the tool wants to pack the address signal as a register either inside or immediately adjacent to the RAM block, and likewise for the output of the other RAM block. If the design considers those registers to be one and the same, then it can't satisfy both requirements simultaneously, and thus uses logic instead of RAM blocks. If so, adding an extra register between the two blocks should help, but obviously will cost you an extra cycle.

(I don't know which FPGA and toolchain you're using, but there was an update to Quartus 18.1 which fixed some RAM block corner cases.)


Sat Aug 27, 2022 10:29 am
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