I am expanding a 20 bit design to 36 bits. You have unsigned characters (9) bits or word data (36) bits.
The rough draft for the 20 bit cpu is 16 opcodes, as 128 x 16 rom.

The rom's fit into 22v10's. Modified the microcode to use 16v8's for Alu I/O, rather than 22v10's.
MMu logic is still up in the air, but the 36 bit CPU looks to fit all on single mid sized PCB. 12" x 10"?
Ben.

Is this using late 70's technology?
Putting any expansion connectors on the board?

More like the early 1980's. I am trying to squeze 3 1970's PCB's into 1 large PCB.
I have rethink the data path again, to get it to flow 8 bits per chip. The pal logic was designed
4 bits per chip using 4 bit wide bit slices.
Does any one make 9 bit bit wide memory
in thru the hole packaging?

Some of the old DRAM chips were 1 bit wide, so they could be combined with 4-bit wide chips to make 9 bits.
There might be a cache tag RAM that is 9 or 10 bits wide. But that is probably not early 80's tech.

Take 5 min break, and I lose my draft.
The design will be similar to a IBM AT ( 6.6 Mhz) and 256kb of ram.
The computer will use 2 56 pin connectors per circut board, under each 16 bit alu.
A 4 bit 2901 will be in the middle. 8" x 11" pcb seems about right for now.
Two data sizes, byte (9 bits unsigned) and word 36 bits.
22v10's will emulate 74F823's and 74827's. (9 bit d f/f and 10 bit buffers).
Ben.

This design is July xx 1984. Other than using CMOS chips, it seems buildable
(4 layer board may be needed for the large power draw) in that time frame. 22v10
's are must since bytes are 9 bits wide.
20 bits is segment size or 256K words of prgram space.
This first version will just have space for the MMU, but no logic to enable it.
Modern chips will replace the 64K x 1 drams used.
Ben.