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 [ 15 posts ] 
 Hexed Computers - 1978 retro computing. 
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Joined: Mon Oct 07, 2019 2:41 am
Posts: 365
I still have to clean up I/O hardware, but for the most part I have the multi-card 32 bit computer design down. Boards #1 & #2 alu cards usimg 2901's. Board #3
Control card. Board #4 front panel & clock timing. Board #5 is the video display, to be designed to give MDA text. 16.257 Mhz video, with the CPU running at .985 uS.
The remaining boards are memory/serial I/O and SDC cards. The cards are using thru the hole components and modern components, but use the timing of parts from the late 1970's.
The instruction set has been tweeked and revised from the experimental versions of few days ago. Serial I/O is set @ 300 baud, for modems of that time frame.
Memory is 128Kb using 16k d-rams. Video is 8x8 or better text display. Programming will use hexadecimal or decimal numbers, with hex display (serial) front
panel designed for it. CMOS 16v8's are planned to be used everywhere as they are low power.
Addressing modes are R,(R),(R+),R)# and #. 7 registers and the normal alu operations and data sizes. Upto 512Kb of memory.
Ben.


Sun Aug 21, 2022 10:11 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 365
I cannot get my video display to run with a MGA clock. I will be using 25 mhz clock with the video card, thus 6.25 Mhz clock master clock.
This would be about 1980's memory speeds with 150 or 200 ns d-rams. Baud rate is still 300 baud, with 74LS224 fifo's for the serial devices.
I will be slowly converting my i/o devices to 16v8 logic, as I have had little luck useing verlog or vhdl versions of the common i/o devices.
Using 100 ns eproms,2901A's,15 ns pals I can have a around a 8 mhz master clock. Faster than that I can only use my FPGA card, 25 mhz master
clock. The master clock is divided by 4 to give me E & Q timing like the 6809.
Ben.


Mon Aug 22, 2022 3:32 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 365
With IRQ's working I now have a working computer, save for a liitle speaker for the bell sound.
Speed is not a issue, set up and hold times are. Some designs route, some don't.
-----
FPGA stats:

Total block memory bits 129,408 / 239,616 ( 54 % )
Total block memory implementation bits 175,104 / 239,616 ( 73 % )

LUT's 2,107 / 18,752 ( 11 % )
REGISTERS 1,095 / 19,649 ( 6 % )
------


Tue Aug 23, 2022 5:50 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 365
Since the 32 bit computer works, can I stretch it to 48 bits with the FPGA ? Yes I can, I did and it does.
I now have a 8/16/48 bit computer. Does this make it 1968 computing? It may not be a ATLAS, but then again
could the the ATLAS fit in shoe box like the DE1?
Ben.


Thu Aug 25, 2022 1:08 am

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1712
Shoebox supercomputing!

I assume your external memory bus hasn't changed width, so what kind of arrangement do you have for the wide CPU and (relatively) narrow memory?


Thu Aug 25, 2022 7:28 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 365
BigEd wrote:
Shoebox supercomputing!

I assume your external memory bus hasn't changed width, so what kind of arrangement do you have for the wide CPU and (relatively) narrow memory?

I just read / write 16 bits at a time. Strange having 3 alu cards on the mother board however. I do have instruction that will multiply by 6 for indexing.
Byte,short (16 bits), int (48) bits. I rather would have a slow 48 bit cpu, than a fast 16 bit one. With the video card,I run at a 6.25 mhz (4 phase clock). 200 ns dram.
A serial version would run at 4.9 mhz, 250 ns dram.
48 bits gives a nice floating point number as 32 bits has proven time and time again too small,6 digits. Pocket calculator 1974 8 digits.
I notice when the IBM 360 was designed, 60 bits width for CDC 6000 and 64 bits for the IBM 7030, so they knew even then it was too small.
Ben.


Thu Aug 25, 2022 10:37 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 365
Nip 78
New Infomation Processor 1978
- Bit slice design
- Solid state memory 16 k dynamic ram
- .960 uS memory cycle
- 1 Meg address space
- Binary and Excess 3 operations.
- 16 Bit data path.
- single level interupts
- 8, 16, 48 bit sized data
- 100 pin bus
- planned 4 mhz LSI version in a 42 pin dip.
- 4 phase clock
- 25.175 Mhz video clock.
- R,(R),(R+),(R+#),(ABS) and imediate addressing modes
- HEX front panel
- Algol friendly

Alu card 4 2901 ALU's and a PAL carry lookahead,MSI TTL ~ 23 chips
Control card 4 PAL's and 3 1024x8 proms.MSI TTL ~ 23 chips
Other cards to be developed.
Ben.


Sat Aug 27, 2022 4:19 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 365
Now .8 uS memory cycle read. 48 bit operand, 5.6 uS.
1978 design ball park timing using 2901's and 82s100's just meet this timing.
Mid 60's core memory was about 2.5 uS cycle time, or 5 us for a normal instuction,
so about the same speed as computer 15 years before.
Ben.


Sat Aug 27, 2022 8:02 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1712
Mentioning a video clock stuck out to me as unusual - do I take it you plan a frame buffer in that 1M address space? And so you have some idea about sharing video and CPU accesses?


Sun Aug 28, 2022 6:30 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 365
BigEd wrote:
Mentioning a video clock stuck out to me as unusual - do I take it you plan a frame buffer in that 1M address space? And so you have some idea about sharing video and CPU accesses?

Quick and dirty text 4K buffer. 0..31,0..127 text frame buffer. FPGA single port ram, separate read/write ports, video read port and writes are a shadow buffer of the
slow frame buffer in memory. Video reads every 4 clocks, the cpu reads/writes every 10 clocks.
A very simple glass TTY. Backspace,New Line,Normal characters work. IBM ASCII 1965, the \ switched with ¬ symbol.
The version that has all the PL/I symbols in the upper case ASCII set. ! is used as bar symbol.
Once developent is done, I may try a graphics mode, but the internal block ram left may be too small to use.
The FPGA is getting rather sensitive in just how things are decoded, change some logic around, poof you don't work any more.
Ben.


Sun Aug 28, 2022 7:56 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 365
Ands a few more 82100's to the design, err CMOS 20V8's. The PCB version of the computer is really starting get power hungery. ~ 2.5 amps per card.
I better order some CMOS 2901 parts. Goes to bed before POOF some thing bad happens at 2 am.


Sun Aug 28, 2022 8:34 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 365
Played with the timing off a 25 mhz clock, I get 800 ns 600 ns and 400 ns, 3 phase clock.
Version #1 (big) 1976. 4K rams. .8 uS 2901 82S100's LSxxx
Version #2 (small) 1979 16K rams .6 us 2901A 82S100's 16L8's LSxxx
Version #3 (fast) 1983 16K rams fast .4 us 2901B 20L8A's 16L8A's Fxxx


Sun Aug 28, 2022 11:15 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 365
Better information on PAL's from MMI, 1978 let revise the design to 1978 specs on paper. Master clock. 8 mhz divided by 5, for a 1.6 Mhz 3 phase clock. .625 uS.
Extra features are Excess 3 math and Double dabble and reverse Double dabble adjustment. This version finshed (ALU/Control segments) other than cleaning
the PAL's up for PCB layout. The FPGA and the TTL version with VGA use a 8.333 Mhz master clock. 35 ns or less PAL's recomened.
Ben.


Wed Aug 31, 2022 6:11 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 365
Revised the timing to be 680 nS from 600 nS, about a 7.14 Mhz clock (2 x color burst). Ben.


Wed Aug 31, 2022 8:35 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 365
Video timing is making things intersting as I only have 25 mhz / n clock for timing.Back to a two phase clock like the 6802. Using 1988 parts,
I can get a 3 mhz clock, but it looks like I will need a 4 layer pcb. I plan to use large number of 22v10's as input register and multiplexer.
This way I only need 3 chips for each 4 bit slice. Input reg and mulx (22v10) , cmos 2901 bit slice and a 74LS173 out put register.
This looks to be doable on a 2 sided PCB, and I can create a 2 Mhz design. I have the 22v10's, but they may be hard to find other than ebay
(china). Ben.


Sat Sep 03, 2022 6:12 am
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