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 FALCON24 - Sketch 
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Joined: Sat Feb 02, 2013 9:40 am
Posts: 1696
Location: Canada
While I was waiting for the plumber to arrive I sketched up the following cpu made up of mostly LSTTL parts. I'm toying with the idea of actually trying to construct it.
It's a 24 bitter. 16 regs. about 30 instructions. Non-overlapped pipeline. I estimate the max frequency to be about 2MHz due to the use of carry chains and four layers of chips in the ALU. It should be about 80 chips for the cpu.


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Robert Finch http://www.finitron.ca


Mon Apr 18, 2016 10:19 pm WWW

Joined: Tue Dec 31, 2013 2:01 am
Posts: 116
Location: Sacramento, CA, United States
I always thought that the "non-standard" word widths were interesting, and have even toyed with the idea of expanding my still incomplete 32-bitter to 36 or 40 bits. Can you explain why so many of the non-power-of-two word size machines have faded into history? It seems to me that they have a lot to offer, especially in that interesting area between 32 and 64.

Mike B.


Tue Apr 19, 2016 3:46 am

Joined: Wed Apr 24, 2013 9:40 pm
Posts: 210
Location: Huntsville, AL
It's been my impression that the widths of early processor were determined by the accepted width of the printable character code at the time of their design. For example, at the time that the 12, 18, and 36 DEC machines were designed, the printable character code width was generally accepted to be 6 bits. A number of other machines, such as the CDC IOPs (12), 6600 (60), and 7600 (60), the Burroughs B5500 series (48+tag), Honeywell 800 series (48) were similarly oriented to handling 6-bit printable characters.

IBM's EBCDIC and ASCII character sets established 8 bits as the standard width for printable characters. IMO, the dominance of IBM essentially forced the industry to move to processor word widths that would more efficiently handle the 8-bit printable character set. In response to IBM's lead, I think DEC and DG responded with architectures (PDP11 and Nova, respectively) that further cemented the 8-bit character as the width for non-arithmetic data. The processor word width wars were over when the majority of microprocessors came out supporting an 8-bit word width.

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Michael A.


Tue Apr 19, 2016 1:11 pm

Joined: Tue Dec 31, 2013 2:01 am
Posts: 116
Location: Sacramento, CA, United States
Yeah, I understand, but that doesn't explain the "other" multiples of eight, like 24, 40, 48, and 56. I know I'm weird, but it looks like there's a lot of underutilized territory there.

Mike B.


Tue Apr 19, 2016 3:25 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1702
I've wondered the same thing, but I think I have an explanation:

These days we mostly see byte-addressable memory, which means that we need to be able to form a word address from a byte address - that's easy if there's a power of two bytes in a word, and difficult otherwise. In earlier machines with word-addressable memory that's no problem - three characters in a word is just as workable as two or four.

I'd guess that we might find other word sizes in DSP machines, where character access is a very low priority.


Tue Apr 19, 2016 7:20 pm

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1696
Location: Canada
Quote:
Yeah, I understand, but that doesn't explain the "other" multiples of eight, like 24, 40, 48, and 56. I know I'm weird, but it looks like there's a lot of underutilized territory there

I had a friend a while back who wanted me to develop a custom 52 bit machine because it matched the number of cards in a deck. Each bit position could represent a card then. A 13 bit byte could represent the suit.

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Robert Finch http://www.finitron.ca


Wed Apr 20, 2016 12:56 am WWW

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1696
Location: Canada
Spending a little more time at it I improved the sketch, eliminating about 20 chips from the design. It should be about 60 chips now. Just about ready for real schematics. I changed the instruction set slightly and allow for 32 regs.


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Robert Finch http://www.finitron.ca


Wed Apr 20, 2016 4:32 am WWW
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