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 DTLC "ditlc" Discrete Transistor Logic Computer 
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Joined: Sat May 28, 2016 10:47 am
Posts: 8
Every once in a while aka when i am up to late, i get the urge to build a computer. out of discrete parts.

My Goals are as follows:

NO dip chips
NO Wire Wrapping

I find soldering through hole components soothing and relaxing, kind of like knitting. Also crazy projects.

I envision a mess of perf board and IDE cables.

Ive been pondering the idea for a few years now and want to start working on something. I dont really know what im doing but im going to take a whack at it and hope i dont end up with a $100 pile of parts and solder that is so fundamentally flawed it will never work.

Since i feel i can program better than i can design and fabricate my design motto is "add just enough hardware to be able to add features in software"

MICROCODE!!!! for instance i have no idea how in the hell to do multiplication and division in hardware logic (AND I DONT WANT TO KNOW) i was reading that you can do multiplication fairly quickly (vs an ADD loop) with bit shifts and ADD.

SO when you fire off the MUL instruction its going to jump to a part of memory (boot strapped in or part of memory is ROM) and get into the LOOP that ADDs and ShiFTs all the right ways to get the answer.

MODULARITY is the plan!! not down to the logic gate but maybe down to each flip flop in the register on its own little bit of perf board then all stacked up :)

Im thinking build a register first THATS MY GOAL!! build a register by christmas (16 bits) [in software chop up number and do 32bit math] its just a bunch of gated D flip flops right? have all the memory on one bus with the control loop enabling registers to read the bus based on the OP code.

COMMANDS: IF, WHILE, IFELSE (cant i just implement IFELSE and have the compiler make IF an IFELSE with NUL just load next instruction as the else?) it seems like i could make modular ALUs as well, have an opcode just be a 4 bit word? thats fed to an ALU control bus and the ALU that is hardwired to that OP code spits out the result and all the others stay silent

Sorry for the long incoherent ramble, hopefully one day i will have a nice project with pictures for you. Thanks for Reading all the way to here. have a good one


Sat May 28, 2016 11:23 am

Joined: Tue Dec 31, 2013 2:01 am
Posts: 116
Location: Sacramento, CA, United States
Welcome Squoril,

You definitely have your work cut out for you, but what you are envisioning is certainly not impossible. My floundering 65m32 design will be destined for an FPGA, and I don't expect it to top 25 MIPS with current hobbyist technology. There is plenty of prior art "out there" for you to study, and I recommend doing so before you jump into the deep end. Maybe you could start with a software simulation of what you want, so you can tailor your encoding and instruction set before grabbing the soldering iron.

Mike B.

Sat May 28, 2016 3:31 pm

Joined: Tue Dec 11, 2012 8:03 am
Posts: 285
Location: California
A recent one that has been making a splash on the 6502 forums is ... microchip/ where he did the whole thing in discrete transistors although with PCBs. Dieter Mueler has material about designing your own ALU at . At the bottom of the page, you'll see links to move around in the Homebuilt CPUs WebRing.

_________________ lots of 6502 resources

Sat May 28, 2016 3:56 pm WWW

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1695
Welcome Squoril! I was just reading a lot of information about the PDP-8 - it was a pretty successful computer, rather limited by today's standards, but the design is very well documented and a re-implementation or an analysis of the machine has apparently been part of several courses and books about CPU design. So if you want to implement a design which is known to work - and has been implemented in the past with diode logic - that's a possible starting point.
"On 18 April of 1970, the first Cuban minicomputer, the CID 201, became operational. It was a third-generation model, with DTL integrated circuits, a 4K memory"

Sat May 28, 2016 9:39 pm

Joined: Sat May 28, 2016 10:47 am
Posts: 8
Thanks for all the advice guys :) love CPUwebring

What would you recommend for a logic simulator?

Sat May 28, 2016 11:32 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1695
If you don't mind proprietary software with an enormous download, then ISIM which is part of Xilinx' free WebPack FPGA software is easy enough to use and capable enough: you can simulate from schematics or Verilog or VHDL. I imagine you get something similar and also free from the other FPGA vendors.

If you prefer open source software, take a look at gEDA:
which includes Icarus Verilog. For diode-based design (if you can't simulate at logic gate level) you'd use ngspice - but this will run very slowly for a larger design. See also the simulators listed at OpenCollector: ... Simulation

If you're a fan of Python, try a search like "logic simulator python" and see what you can find.

Sun May 29, 2016 2:07 am

Joined: Sat May 28, 2016 10:47 am
Posts: 8
i found this program logism, which seems perfect, however i found a bug (i think) where i cant have the input and output pins of my register module connected on the common bus, even though there should be no unstable state unless you enable read AND write at the same time on the register, is this a fundamental bit of knowledge im missing?

the design im playing with is a simple gated D latch (S/R latch with some extra gates) with and gates for read enable on the output

ill try and add a picture to show you what i mean

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Sun May 29, 2016 12:25 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1695
Is it when you have more than one register on the bus that you have trouble?

In effect, you have a wired-OR bus, I think. Things which are not currently driving are in fact driving zero. For a logic simulator it's usually not handled to have multiple drivers on one net, so instead you might need to put in the explicit OR gate. All the drivers go into the OR, and the output is your bus, and can then feed all the readers.

Hope this helps.


Sun May 29, 2016 12:33 pm

Joined: Sat May 28, 2016 10:47 am
Posts: 8
even just the circuit shown will throw an error when trying to load a 1 or try to read the 1 (that i loaded with the output wire cut)

im getting the feeling logism simulates with flow not states, i get an error trying to feed a signal from an input pin to the output of a gate and visa versa

Sun May 29, 2016 12:42 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1695
yes, in effect you have two things driving one net: the AND gate, and the external input. You should still be able to put in the OR gate as a workaround: one input from the AND and the other input is your input - which must always be zero when you're reading the register.

Sun May 29, 2016 12:45 pm

Joined: Sat May 28, 2016 10:47 am
Posts: 8
found a setting i can tweek so i can make the gates ignore bits coming to their output from a pin (changed output to floating/1 from 0/1) the OR gate seems to be making things happier

doing some more testing but not sure about being able to make one pin in the module be I/O maybe it needs to be 3 state?

EDIT: success all bus lines with pins must have input pins set to the x state for it to work, just simulated storing a bit in x register, then copying to y register

Sun May 29, 2016 12:57 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1695
yes, anything bidirectional is likely to mean that you need 3-state logic.

going back to your diode machine: you probably can't build a tristate driver with diodes. So wired-OR is (I would guess) the mostly likely bus structure.

Sun May 29, 2016 1:04 pm

Joined: Sat May 28, 2016 10:47 am
Posts: 8
probably, i expect the simulated is going to vary from the hardware. Successfully simulated 3, 4 bit registers, common I/O bus, 2 bit address bus and a R/W bit, just added a copy bit, so 8 bits (a byte yayyy) 4 bit op code and 4 bit data bus simulated basic register control.

Sun May 29, 2016 2:06 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1695
That's progress!

Sun May 29, 2016 2:17 pm

Joined: Sat May 28, 2016 10:47 am
Posts: 8
discovered that someone forked logisim and is continuing development under the name logisim-evolution

also think i have identified all the bugs i have found so far (resolved the previous bug above by setting the defined states of the final logic gate before a bus to floating/1 versus 0/1)

the latest one thats popped up is an oscillation error in the register D-latches that occurs when the bus changes at the same time or one "tick" after the write enable on the register goes low, somewhat of a race condition going on i think its called. My thought is in the later revisions the control logic will have to have logic delays to give the registers to disable write before letting the register bus change

Wed Jun 15, 2016 5:59 pm
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