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 74xx based CPU (yet another) 
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Joined: Sat Feb 02, 2013 9:40 am
Posts: 1531
Location: Canada
Quote:
As for the writeback stage, without getting into too much detail, it's common to build register files with synchronous RAM in an FPGA. This means you need a clock pulse (usually the inverted cpu clock) for the RAM to do a write and to register the read address and perform the read. So that means you need to have the value you want to write early in the cycle, hence needing the writeback stage. Further, the read value is only available very late in the cycle, so it would be very tight to add muxes after the register file, and often then you would put all the muxes at the beginning of the execute stage instead.
One can also extend the pipeline by a cycle or two and use additional results forwarding after the writeback-stage to compensate for a two-cycle read latency of block rams. Data ends up coming from results forwarding latches while the register file output is still invalid. This allows the use of the regular clock, no inversion needed, and the value to write can be later in the cycle.

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Robert Finch http://www.finitron.ca


Thu Dec 10, 2020 4:18 am WWW

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1647
Drass wrote:
...It seems to me that you can place the muxes at either the beginning of the execute stage or at the end of the decode stage, for example, and this works whether you have a WB stage or not. Each approach simply affords a different tradeoff in terms of how delay is distributed between pipeline stages, that’s all.


There is, or can be, another consideration... in chip design, especially back in the 80s and before, interconnect was very limited. So, moving a mux fore or aft of a flop will change the wiring. It'll also change the number of flops. One of the big decisions in laying out a VLSI CPU was how many grids per bit in the datapath: each bit needs to carry local and global traffic, in the worst case from one end of the datapath to the other. You can see in the 6502 how careful they were to have limited busses running along each bit slice.


Thu Dec 10, 2020 9:02 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 273
Register files with FPGA's can be tricky, because details seem change from every device
and always diferent with every brand.


Thu Dec 10, 2020 4:34 pm
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Joined: Fri Mar 22, 2019 8:03 am
Posts: 328
Location: Girona-Catalonia
robfinch wrote:
One can also extend the pipeline by a cycle or two and use additional results forwarding after the writeback-stage to compensate for a two-cycle read latency of block rams. Data ends up coming from results forwarding latches while the register file output is still invalid. This allows the use of the regular clock, no inversion needed, and the value to write can be later in the cycle.

That's a good point, and this also makes me realise that more pipeline stages are not a complicated thing, after all. It turns out that I am already using a sort of "extended pipeline" for the purpose of computing the status register flags, except that I hadn't realised this could actually be regarded as that.


Fri Dec 11, 2020 9:03 am

Joined: Sat Nov 28, 2020 4:18 pm
Posts: 123
So, I am guessing you are taking a break, and that's okay.

I do want to say that I am excited about this project and I am hoping that, after your break, this project will reach the point that I can also build one. I don't think rj16 or rj32 will end up with a discrete logic implementation, but maybe I can build a CPU74 to satisfy that itch.

I think you should run with your impressive 30 MHz 3 stage pipeline processor and see how it goes. It's hard to make a PCB design that will actually hit 30 MHz but I wouldn't be discouraged by that. Just expect some iteration and maybe an oscilloscope purchase.


Fri Jan 22, 2021 1:29 pm
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