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 ben's20 bit cpu. 
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Joined: Mon Oct 07, 2019 1:26 pm
Posts: 43
Hi Ben, I'm looking for a simple OS for my Kobold computer. It's a computer with 20 address lines, so around the same size as yours.

That OS that you use, does it have free C source ? And/or did you make it yourself ? Would you recommend it ?


Sun Jun 14, 2020 6:32 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 317
It is my own os, but written in my own language so it rather not portable to other
machines because of the way subroutines are called. Frame based rather than stack based.
The compiler and the assembler are both written in C ("USS Enterprise NCC 1701. No bloody A-B-C-D or E!" Scotty).
The os is a simple CP/M style os, using a block size of 1526 bytes (3 512 byte sectors).
I have a fat table of one sector and directory of one block. This gives ample space for
the I/O at the time (1975-1980) using GCR. The simple OS is placed in
the last 64Kb of memory and the bottom memory is used for programs.
I have 1KB bios that provides the basic I/O read char / write char / read block write
block,boot from paper tape,boot from disk.
The OS is written in 4 segments, so I have bootstrap version and the DOS using
the same code, with just a few routines in the main body.
Ben.


Sun Jun 14, 2020 7:24 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 317
Here are the files. This is for a 8/16/32 bit cpu
This software requires a CPU with a long branches
and set ac to 0/1 on condition codes.

bengol.zip is the bengol compiler + microcode test
cpu.lst (txt) is the microcode roms
benos.zip is the os written in bengol
The bengol compiler is being revised to make it easy to port
simple c programs. { after a function define C like operands
other wise a algol like syntax begin end if eif else endif while repeat
do until. Structures are defined as offset to a array
Ben.


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Sun Jun 14, 2020 8:46 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 317
Now upgrading the hardware this week, for the 20 bit cpu. Moving the SD card from the DE1
to the expansion bus using Sparkfun's SD card adaptors, once FedEx delivers them.WOW 2
1970 IBM 2315 disk cartridge drives (software emulated). 32K words ram make this a MID SIZED
micro computer. ( still need to add more serial ports and printer ).

Tweeking the hardware for BCD floating point routines, and some general software revsions
as well.
I have come to the conclusion that 12K (words) is needed for the OS and I/O buffers+ Stack.
24 K (words) is needed for program space. CP/M got away with a small footprint by having 128 byte
sectors and the user program handles buffer and stack space. Flex (6800) had 256 byte sectors
and a 8K footprint. Apple and the other machines had a 'ROM BASIC' O/S.
12/16 bit machines had fancy DMA Discs that swapped core and disk to give virtual memory
and often timesharing in 16K words.


Thu Aug 06, 2020 5:32 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 317
Hardware has added a micro SD card, so now I have a "two floppy" system.
Decoding has been tweeked, to be faster. Still have no idea what to set the
core memory speed (TTL) for ~1974. ~ 6 amps for 20 bit alu card. .1.0 us cycle time?
LS/MOS memory version ~ 1975 .5 to .7 us?
Toying with a 24 version the cpu, but it has a few glitches still. Simple decoding
and carry lookahead makes it faster. 2 alu cards makes for a better layout.
Now back to debugging.


Sat Aug 29, 2020 3:22 am

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1678
Location: Canada
Quote:
CP/M got away with a small footprint by having 128 byte
sectors and the user program handles buffer and stack space. Flex (6800) had 256 byte sectors
and a 8K footprint. Apple and the other machines had a 'ROM BASIC' O/S.
12/16 bit machines had fancy DMA Discs that swapped core and disk to give virtual memory
and often timesharing in 16K words.

I can't believe how compact the OS is of some earlier machines.

Quote:
core memory speed (TTL) for ~1974. ~ 6 amps for 20 bit alu card. .1.0 us cycle time?
LS/MOS memory version ~ 1975 .5 to .7 us?
6 amps just for the ALU? How many for the whole machine?

_________________
Robert Finch http://www.finitron.ca


Mon Aug 31, 2020 3:52 am WWW

Joined: Mon Oct 07, 2019 2:41 am
Posts: 317
This is just paper design, TTL chips run at about 50 ma for gates, MSI 100 or 150 ma per chip.
A 4 bit slice is about 1.25 amps for the data path. I guess about 20 amps with a serial port
and 8K (words of core). With core memory, the alu took most of the power. After core memory
memory took most of the power. Add a few amps for blinking lights ~ 1973. 74LS came out I
guess about 1975, with cheaper $10? 4k drams.
The fpga card I have uses about 1 amp.
Ben.


Mon Aug 31, 2020 7:20 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 317
Floating point routines have been coded for a larger 24 bit cpu, with a 2901 alu (emulated fpga).
What software I have needs be rewriten for 2 words floating point. A 40 bit floating point
serves my needs better than 48 bits and looks be simplier if I have word size
operations (40 bits) in hardware.
I plan to use 3 eproms for microde
and 22v10's to decode the proms. 22v10's will be ever where other some small gates
for the clocks and simple logic. The 22V10's have 20 ns delay and are Quarter power
thus replacing 74LS MSI makes sense, mostly for better PCB pinouts.
Exact timing will depend of the speed of the eproms, but still core memory speeds and timing.
Here the dead memory write cycle can be used for the second ALU pass for 2 word instructions.

The memory model can have up to 512Kb of ram, but only 32 KB for the O/S and stack and 128KB for programs is planned for the system. 4K rom will be for BIOS and bootstrap routines.

128KB is the same 32K words so I have computer similar to the big iron of the late
1950's.
I expect to have someting around mid January, running on DE1 FPGA computer.Ben.


Fri Dec 11, 2020 8:13 am

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1678
Location: Canada
One of the nice things about using an FPGA is components can be made as wide as needed one does not have to worry about pin limits. The 2901 ALU could be 48 bits wide. Are there other 29xx series chips being emulated? Nostalgia moment. I remember drooling over some 2901’s as a teenager a bit pricey for my budget. I found some 74S181’s instead. Got some 29xxx rams floating around someplace. I used to have the data-book for the 29xx series.

_________________
Robert Finch http://www.finitron.ca


Sat Dec 12, 2020 4:39 am WWW

Joined: Mon Oct 07, 2019 2:41 am
Posts: 317
The 2901 is a bit tricky emulate in a FPGA because it uses tristate logic on some of the pins.
In my case I don't need a 100% emulation, and have a modified interface to the 2901 alu section
and just have the features I use. That saves me two bits of microcode rom. Q is a scratch register
only and
Code:
B = A op B
is not used.
A real 2901 model is floating around on the web, but have not seen anyting else. I suspect
anybody that used a bitslice computer have long moved to a FPGA verson, or switched something more modern. Extra RAM can be added to the 2903.


Sat Dec 12, 2020 6:42 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 317
This design is way to complex for me as the PCB's will be really big.
The the demo front panel is small. 10 inches x 5 inches.
I have some ideas's for other
architectures, but I can't make up my mind what to build.

A RISC design has the advantage any roms are programmed via the front panel.
The disadvantage is having no stack or frame pointer and no IRQ's of any kind.
~ 41 MSI chips TTL logic

The CISC uses 22v10 and EEPROM's thus requring me to keep my old computer
around so I can program said devices when I build the hardware a few years down the road
~ 22 chips but 6+ 22V10's and 2901's.

cpu175.png


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Tue Dec 21, 2021 4:53 am

Joined: Wed Apr 24, 2013 9:40 pm
Posts: 210
Location: Huntsville, AL
oldben:

oldben wrote:
The 2901 is a bit tricky emulate in a FPGA because it uses tristate logic on some of the pins.
It's true that it's been a few FPGA generations since FPGAs actually included on-chip tri-state busses and drivers. However, I use "tri-state" busses in my current FPGAs, and the synthesis SW automatically translates that desired behavioral description into a structure supported by the target FPGA's architecture. Without actual on-chip tri-state features, modern FPGAs / CPLDs synthesis tools will translate those behavioral descriptions into AND-OR logic arrangements. On modern FPGAs, the number of loads on the tri-state bus will determine the width of the OR gate, and drive the number of logic levels needed to implement the wide OR gate.

Thus, I think that you're selling more modern FPGAs and CPLDs short if your concern regarding the logical implementation of "tri-state" busses and signals is the reason why you're avoiding their use in your current designs.

_________________
Michael A.


Thu Dec 23, 2021 1:33 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 317
I tend to avoid things like 'surface mount' and programing languages that end in # or ++ as well
as well as VHDL and VERLOG. The latter two I see as both crap when you can program a PAL with a nice simple
discription. WINDOWS , LINUX and ANY MODERN CPU are also on my IT IS CRAP list as they keep changing
stuff around, and breaking hardware and software I use.

CARE to fix why my TL866II plus programmer failes to work, with a cryptic error message in Chinese.
USB is the latest driver. Something about not finding a hardware timer when programming the device.

The real reason I avoid new stuff, is do to the fact nothing new works with the old stuff,
or at low res screens. I like 80 x 25 text screen because I can see it clearly, full screen not a tiny window.
My favorite text editor crashes on this machine. BUGS BUGS and more BUGS.

My goal of using a FPGA is to emulate a design with OLD LOGIC - 2901, 74XXX, 6850, before building it in real hardware. Here a D F/F must have both preset and clear, modern FPGA 's don't support that any more
or 5 volt I/O.

I wish to use computers, not work around bugs or missing features for me or play click the mouse.
Please feel free to substitue the Politicaly Correct term of the day for 'crap'.
Ben.


Thu Dec 23, 2021 6:02 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1690
It's a series of trade-offs. These days we have fast cheap computers and fast cheap capacious FPGAs, and the price of that is that the design (and implementation) isn't quite ideal for our purposes. The spirit of engineering, of course, is to be creative and productive in the face of constraints.


Fri Dec 24, 2021 6:18 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 317
... And you can program a PI to emulate almost any vintage machine.
Ben.


Fri Dec 24, 2021 6:57 pm
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