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 G6A-RISC Relay Computer 
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I made all required updates to the Logisim model, and finally managed to get the a full square root computed in logisim according to the code in my previous post. I do not know what size of projects logisim is supposed to handle, but I think this one is particularly big. It's not that this cpu is particularly complicated, but it's a relay cpu and everything in the logisim model tracks down to single relay boxes, modelled as a couple multiplexers per relay. With a total of 879 relay boxes according to logisim, it can be observed that the entire model is pretty big.

On my 12 years old mac, the logisim model runs at a rate of half instruction per second (or one instruction every 2 seconds). Setting up 'Tick frequency' doesn't do anything because I guess that it is already running at the max possible speed. So the entire computation of the square root of 2 takes about 20 minutes to complete. This is a screenshot I took of that epic instant where the root was already computed and the result still visible in the r0:r1:r2 registers:

Attachment:
Screen Shot 2020-02-07 at 10.45.55.png
Screen Shot 2020-02-07 at 10.45.55.png [ 222.82 KiB | Viewed 2502 times ]


The orange, purple and red circles show the register values with 11 digits of the square root of 2 (1.4142135623)

0x0141 in R2 (orange)
0x4213 in R1 (purple)
0x5623 in R0 (red)


Fri Feb 07, 2020 10:26 am
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Splendid!

I'm reminded, for some time I had an interest, a joint interest with revaldinho, in the Bombe and how to model it in hardware, or in verilog. Much like your relay circuits, I imagine, there's a difficulty of resolving electrical circuits bidirectionally. I did at one point have a sketch of an idea how to do that, but possibly I never wrote it down, and anyhow it wasn't tested. Is there a difficulty for you, or could your designs readily be captured in, say, verilog? (Or another HDL, of course.)


Fri Feb 07, 2020 10:47 am
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BigEd wrote:
Splendid!

I'm reminded, for some time I had an interest, a joint interest with revaldinho, in the Bombe and how to model it in hardware, or in verilog. Much like your relay circuits, I imagine, there's a difficulty of resolving electrical circuits bidirectionally. I did at one point have a sketch of an idea how to do that, but possibly I never wrote it down, and anyhow it wasn't tested. Is there a difficulty for you, or could your designs readily be captured in, say, verilog? (Or another HDL, of course.)

Hi Ed,
I do not have a bidirectional model for the relays, so I can't really give an answer for this question. I just have modelled several versions of them to mimic the several possible connection scenarios of the double contact mechanisms, but they can't act bidirectionally in the model. I do not use the property of contact bidirectionally in my cpu model. In the design, I adopted the policy of inserting a diode (in fact a buffer gate in logisim) in all instances where two or more wires will connect to the same line or bus. The logisim model would still work with some of these buffers removed, but the diodes are required in the real thing. This means that there's a lot of assumptions of correctness on my cpu model and if I missed something, the real thing may still fail due to unanticipated back currents.

Another problem is that propagation steps are not correct at all in the model. Relays have zero propagation delays for signals that travel along already stablished contacts, but the model ultimately uses logic gates, which have propagation delays in all cases, even through supposed relay contacts. So the model is very far from perfect. Again, a lot of the differences between the model and the real thing must be incorporated in some way in the design itself by thinking about what relays would actually do, rather than just looking at what the model exactly does.

If the Bombe device did not use the bidirectional property of relays I assume that you may still be able to produce a working model of it. Otherwise, I can't say at the moment whether a proper relay model is achievable in logisim or other simulation platforms. Even if a bidirectional kind of device is possible, I doubt that it can be made propagation time accurate.


Last edited by joanlluch on Fri Feb 07, 2020 7:30 pm, edited 1 time in total.



Fri Feb 07, 2020 7:26 pm
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Ah, you're in the clear then, with your (forced) unidirectional signal transmission.

Indeed, the Bombe (with the diagonal board) is bidirectional in nature. So it needs, I think, to be modelled with inserted clocked stages, and it will have to take some clocks to converge to the physical state. I fear it's not a very clean or clear transformation to perform.

But, happily, this is not your problem! With unidirectional logic, it should be amenable to modelling in an HDL, which would give you a faster simulation. Although your diagrams are a great documentation, in a way which HDL is unlikely to be.


Fri Feb 07, 2020 7:30 pm
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BigEd wrote:
With unidirectional logic, it should be amenable to modelling in an HDL, which would give you a faster simulation. Although your diagrams are a great documentation, in a way which HDL is unlikely to be.
So far, the combination of the software simulator and logisim works great for me.

The software simulator is made in a compiled language, so it's very fast. The full execution report appears at the very same instant I hit the enter key. Since it is all plain text I can study what happened instruction by instruction. If needed, I can also run the simulator in the debugger, so this allows me to place breakpoints for example when the simulated PC hits a particular value, or the memory address register hits a memory location, or whatever condition with register values or others, so that for example I can look at which were the contents of memory at any specific step in the execution of the program.

On the other hand, the logisim graphical representation is great to have a more down-to-metal vision. It's a lot more tedious and sluggish at executing programs but that doesn't really matter. Its purpose is testing the correctness of instruction execution in the hardware model, not the correctness of the actual program being run. By the time I enter a program for execution in logisim, I already know that such program is correct. Since I have the execution report including the register values at any given step, I am able to visually match them as the logisim execution runs and in case any difference is produced, I can determine the instruction that didn't work as expected.


Fri Feb 07, 2020 9:53 pm
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Oh, that's great - a great design flow!


Fri Feb 07, 2020 9:57 pm
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It's distracting that this thing will perform the square root of "2" in below 2 seconds: https://youtu.be/_j544ELauus (starting at 13:03) :shock:


Sat Feb 08, 2020 12:52 pm
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I wonder how many instructions it executed? No more than 20, I would guess by the sounds. (Probably not a reliable guess!)


Sat Feb 08, 2020 4:33 pm
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BigEd wrote:
I wonder how many instructions it executed? No more than 20, I would guess by the sounds. (Probably not a reliable guess!)

Yes, that's totally awesome. It's clear that there is specific hardware implemented there just to compute multiplication, division and square root. I'm pretty sure that for these common operations, the computer does not follow a 'subroutine' made of instructions in the way we currently know them, but a hardwired 'sequence' of algorithmic events that lead to the execution of the square root.

I also found this video that maybe helps to explain it https://youtu.be/fnmj9EzKgtg It's a guy performing a square root in a mechanical calculator by only using additions and subtractions. Interestingly, the procedure he follows is identical to the HP algorithm that I showed above and I implemented in my relay computer assembler.

So, back to the Japanese relay computer. That computer has a word size equivalent to the width of a floating point number, so I believe the total number of 'cycles' (not instructions, in fact) used, is the total number of required subtractions/additions. After looking at the algorithm, it looks that the result of sqrt(2) = 1.4142135 requires (1+1)+(4+1)+(1+1)+(4+1)+(2+1)+(1+1)+(3+1)+(5+1) sub/add operations, so a total of 29 cycles assuming one addition is used for counteracting the extra overflowed subtraction per digit. Or better yet, maybe it uses only (1)+(4)+(1)+(4)+(2)+(1)+(3)+(5) = 21 cycles, if there's a way to detect subtraction overflow ahead of it happening for every digit, thus avoiding the 8 counteracting additions. Interestingly, 21 cycles is very near your estimate based on watching the video, so that's probably it (!!)


Sat Feb 08, 2020 5:42 pm
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Aha, that seems like it could be a fair saving, if you had an instruction (or a micro-instruction) which was 'subtract if you can' - it leaves the accumulator unchanged if the subtraction underflowed. That should be easy enough, as it just means suppressing a write back.


Sat Feb 08, 2020 7:46 pm
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BigEd wrote:
Aha, that seems like it could be a fair saving, if you had an instruction (or a micro-instruction) which was 'subtract if you can' - it leaves the accumulator unchanged if the subtraction underflowed. That should be easy enough, as it just means suppressing a write back.
Don't give me ideas...


Sat Feb 08, 2020 7:49 pm
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