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 rj16 - a homebrew 16-bit cpu 
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Joined: Mon Oct 07, 2019 2:41 am
Posts: 256
Having the PC as part of the general purpose register set, made sense for a CPU like the PDP 11, but in most computers I can think of had the PC as special logic path
like a PDP/8. or in core memory 0000(8) like the PDP5. The IBM 1130 computer had index registers but they were stored in main memory as well. Immediate operands are
rather late software concept; 1970's with the PDP 11 and 4/8 bit micro computers having it in hardware.
Ben.


Tue Apr 20, 2021 4:49 am

Joined: Sun Dec 20, 2020 1:54 pm
Posts: 73
I think it makes sense if you have enough silicon to implement a dedicated adder for the PC_NEXT, so you need to move PC into the ALU like if it was a general purpose register.


Tue Apr 20, 2021 11:59 am

Joined: Sat Nov 28, 2020 4:18 pm
Posts: 123
I did put some more thought into keeping the PC as a separate register. I could maybe do it. I would need to shuffle things around to make a jump instruction again.

The issue is that I keep finding reasons to be unhappy with the current instruction set and keep reworking it to be better. Maybe it's improving, but maybe I am just shuffling the problems around. At some point I just need to say "good enough" and get this thing finished. I think it will be interesting to see if making the PC a programmer addressable register will be useful. I haven't worked with a computer with that feature before.

What I currently plan to do is just make the PC programmer addressable, but otherwise it will be implemented the same way, with a dedicated incrementer for the next PC value. If the PC is written to, it will raise the jump line, but that jump line will originate in the address muxes in the register file (though for jal / call I will need to also raise the jump line).

Anyway, the next video is up. I implement skip. It turned out easier than I thought, though there was some bugs I had to fix after the episode when I updated the test cases. I also forgot to talk about why I only need 6 conditions and I can make all the other conditions with them. I will cover that stuff in the intro of the next video.

[027] Conditional Skip! https://youtu.be/qoSirAV3k_U


Wed Apr 21, 2021 12:25 pm

Joined: Sun Dec 20, 2020 1:54 pm
Posts: 73
rj45 wrote:
The issue is that I keep finding reasons to be unhappy with the current instruction set and keep reworking it to be better


Eh, it took me five years of keeping reworking and polishing before the definitive ISA ever, the one which is not perfect but which at least makes me happy :o

Here we have a local saying "you can pull here and there as long as you want, the bed blanket is always short", it means there are compromises, you can only find a sub-optimal solution.


Wed Apr 21, 2021 12:49 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 256
I have allways grumbled about IBM for giving us 16 bit words and bytes, 18 bits was standard, The next size is 20 bits, and a simple ISA workes for that size.
I was working on a 10/20 bit computer but shifted ideas to 16/32 bit computer with 20 bit addressing. Of all the 16 bit computers I have seen the IBM 1130 was the most computer like with the others more control oriented cpu's. The PDP 11 is a specal case design.
With the advance of FPGA's one really can build what ever size they like.


Wed Apr 21, 2021 8:00 pm

Joined: Sun Dec 20, 2020 1:54 pm
Posts: 73
oldben wrote:
With the advance of FPGA's one really can build what ever size they like


Theoretically yes, practically no. BRAM and resources are always 2^n power.

For a Tr-RAM I would like to have a word of 37 bit, I can simulate on TI-NA (it's like pspice but it also support digital things) but if I want to implement something then I have ho use 36 bit, composed by 9 circuits of half-byte (a nibble is 4bit) because that's what I find on the market.


Wed Apr 21, 2021 8:16 pm

Joined: Sat Nov 28, 2020 4:18 pm
Posts: 123
Yeah, I must say, if I had 20 bits instead of just 16 bits, fitting everything would be a heck of a lot easier task. I wouldn't have to bit pack quite so much in order to make the opcode fit and have reasonable immediate sizes. Plus 20 bits is 1 MB, a very reasonable memory size for a hobby computer, and a fairly useful integer size too.

But well, multiples of 8 bits tends to be expected. C also expects 8, 16 or 32 bits. So :cry:


Wed Apr 21, 2021 9:46 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 256
A 22v10 could be programmed as 3 bit alu.
0 ADD A+B
4 SUB A-B
1 AND A&B
5 SL shift B
2 XOR A^B
6 LOAD A
3 OR A|B
3 SL shift B
CN+3 carry out add/sub
logic C+0 | F1 |F2|F3

Todays ALU's are 4 is four bit wide, the real reason you have no 18/36 bit CPU's after about 1975.


Thu Apr 22, 2021 5:55 am

Joined: Sun Dec 20, 2020 1:54 pm
Posts: 73
if we had opcodes in the size of 4*n, n={1, 2, 3, ... }, we would need %4 arithmetic for pointers.
Umm, interesting, and theoritically feasible :o


Thu Apr 22, 2021 8:27 am

Joined: Sun Dec 20, 2020 1:54 pm
Posts: 73
What the wiki says about 12-bit (4x3) computing :D


Thu Apr 22, 2021 8:39 am

Joined: Sun Dec 20, 2020 1:54 pm
Posts: 73
4xn can also represents 2^k, why base4? Because hex is base4, and for example 9 bits are not divided in half and will look ugly in *HEX*, that's why :lol:

hex'set={0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F} -> 16 chars, 4 bit is perfect to identify each char

Code:
       4*n    2^k
       n=?    k=?
  4     1      2
  8     2      3
 12     3      _
 16     4      5
 20     5      _
 24     6      _
 32     7      6
 36     8      _
 40     9      _
 44    10      _
 48    11      _
 52    12      _
 56    12      _
 60    13      _
 64    14      7


Thu Apr 22, 2021 8:49 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 256
12/24 bit cpu's could be divided into octal for easy decoding by eye. Front panel debugging is not often done, but it is handy when something goes
bad with the computer, or you do a dumb programing error.


Thu Apr 22, 2021 8:06 pm

Joined: Sat Nov 28, 2020 4:18 pm
Posts: 123
You know what, I implemented the change to the PC and I don’t like it. DiTBho, I think you’re right, it puts dependencies between several modules that didn’t have them. And I am finding it’s making debugging harder too. I think I am going to roll it back.

I was trying to fix having 3 instructions in the large immediate with no registers format. Imm, call and jump. I need 2 bits for 3 instructions and I can’t think of a fourth instruction to put there. Maybe a long call? Maybe syscall?

Anyway, I don’t need to solve it now. I think instead I will dive into microcode.

I think this time with the microcode I am going to extract the hardwired logic into a separate module, then have a bit in the microcode control a mux that switches the control lines from the hardwired logic to the microcode. Then I can incrementally replace the hardwired logic with microcode and be able to run the tests at each step to make sure nothing breaks. And I will just start the microcode from scratch, instead of generating it from the logic.


Sat Apr 24, 2021 2:39 am

Joined: Sat Nov 28, 2020 4:18 pm
Posts: 123
Next video is up. I switch over to microcode, which went super smooth compared to last time. I didn't need to extract the old logic into a separate circuit, I could incrementally replace it control line by control line.

[028] Microcode! https://youtu.be/WBe4WEOjlK8

So.... what to do next?


Sat Apr 24, 2021 6:36 pm

Joined: Sat Nov 28, 2020 4:18 pm
Posts: 123
So.... I think I am going to make a front panel out of an HDMI monitor. I spent a few days playing with the VGA output in Digital and I got a prototype working. Not sure if it will work on my FPGA but it should. I also figured out how to display text and hex numbers to display lots of debugging info with das blinkenlights :) Should hopefully be a fun few episodes :D

Eventually I can create a retro GPU out of it. A scrolling tilemap and a few hardware sprites maybe.


Thu Apr 29, 2021 3:06 am
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