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Joined: Sat Feb 02, 2013 9:40 am
Posts: 1531
Location: Canada
Latest Fixes:
The flag to update the register file was not being set for the CSR instruction. This caused a following instruction to incorrectly read from the register file.
A bit indexing operation was left off a variable causing the entire value to be written with zero. This caused all addresses in the memory controller to be forced to zero.
The address width size (32) was begin used in a few places where it should have been the maximum width (64). This led to some values being truncated.
The letters were transposed in the TLB write signals leading to writes to the TLB failing.

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Robert Finch http://www.finitron.ca


Sun Sep 05, 2021 5:06 am WWW

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1531
Location: Canada
The watchdog timer exception was occurring during startup as the DRAM takes much longer to initialize than the watchdog timeout. A bit was added in control register zero to enable the watchdog timer rather than having it enabled all the time.

On the FPGA the core runs from $FFFC0300, the start address, to $FFFC0324 then jumps to the exception handler routine address. From there it gets a TLB miss. I do not know why it jumps to the exception handler address. I dumped the cause code field and there are no cause codes being set. The only other source of an exception is an unimplemented instruction. So, now I put code in to dump the unimplemented instruction flag.
It turns out that the unimplemented instruction flag is set for almost every instruction. How it is being set is a mystery. I decided to get rid of the flag and just set the cause code in the reorder buffer to indicate an unimplemented instruction. This makes an unimplemented instruction exception consistent with other exceptions.

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Robert Finch http://www.finitron.ca


Tue Sep 07, 2021 5:36 am WWW

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1531
Location: Canada
Moved the execute module back into the mainline module. It was not working very well as a separate module. Having the code in the mainline trims at least one clock cycle off the execution of every instruction. The execute code was also split into results calculation and registered variable updates. The results calculation was moved outside of clocked logic to a combo logic block.
Finally got to the point of LED output in SIM after fixing numerous small errors. This is going through a segmented and paged memory system. Several pages of memory and IO need to be mapped and the segment registers setup appropriately before output to LEDs can be done.
Some progress was made getting the core to work in the FPGA, it runs much better now but still does not lite the LEDs yet. Something is amiss with the micro-coded instructions as they were encountered during the FPGA run, but did not work correctly. The PUSH and ENTER macro instructions were encountered.

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Robert Finch http://www.finitron.ca


Thu Sep 09, 2021 4:32 am WWW

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1531
Location: Canada
Tentatively added two more groups of compressed instructions. The CI12 group is a group of 64 12-bit instructions that can expand out into a 36-bit instruction. The CI12 group is a 64-entry lookup table. The CI16 group is similar. It is a group of 1024 16-bit instructions that expand to 36-bits using a lookup table. The lookup tables are mapped as the last two 16kB pages of memory and are accessible with store instructions. The core now has four different instructions lengths. 12, 16, 20 and 36 bit.
Latest Fixes:
The commit flag was set prematurely for branch instructions causing all branches to fail, they were skipped over. This issue was created when the execute code was merged back into the mainline code.

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Robert Finch http://www.finitron.ca


Fri Sep 10, 2021 5:38 am WWW

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1531
Location: Canada
The address output to fetch an instruction cache line was not being truncated to the cache line address. This had little impact on the core working and likely would only be an issue if branching into the middle of a cache line.

Spent some time experimenting with the memory request fifo. Memory loads and stores are not happening while running in the FPGA. But obviously instruction fetch is working. So, there is something amiss in the path between executing the load or store and transfer of the operation to the memory controller (bus interface unit) BIU. Since this is working in SIM that leads me to believe there is a difference between SIM and SYNTH for some component. I tried substituting the fifo used for the uart in place of the memory fifo and found out the uart fifo had a bug in it. The number of bits for the fifo count was off by one. I’ve updated the uart fifo.

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Robert Finch http://www.finitron.ca


Sat Sep 11, 2021 3:08 am WWW

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1531
Location: Canada
Backed out the support for 12 and 16 bit compressed instructions. With the additional logic required it could not PAR (place and route) as fast as I am willing to wait. After running PAR for about 12 hours I stopped it. They may make it into a final version, but for expediency they are out at the moment.

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Robert Finch http://www.finitron.ca


Mon Sep 13, 2021 6:28 am WWW

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1531
Location: Canada
The following is OT for ANY1.

Created a program to run on a FTDI VNC2 chip. I had to get used to the vendors toolset. This chip is being used to get a USB keyboard or mouse interface. It supports two USB ports and translates between USB and uart signaling. There is only one uart port. Since there is only a single uart port and two USB sources, the uart port is fed bytes of data in ascii hex format with a ‘K’ prepended for one port and a ‘M’ prepended for the other. The serial port driver in the FPGA will need to separate the two streams of data. Fortunately, this is a low speed interface.

Not sure at this point how to breadboard the circuitry. If I put the FPGA module and FTDI chip modules into a solderless breadboard its unlikely that they would be removable at a later point in time. A lot of force is required to get the modules into the breadboard. I may prefer to make a PCB to connect the modules.

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Robert Finch http://www.finitron.ca


Thu Sep 16, 2021 5:20 am WWW

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1531
Location: Canada
Between bug fixes I have alternated between watching TV and working away in the background on ANY1 version 4. Version 4 is going to be more like the PowerPC in nature, using multiple condition code registers with the ability to update cr0 and cr1 by instructions. I hope to reuse the rfPower code when developing version 4. Version 4 will use fixed 41-bit instructions, three packed into a 128-bit bundle. Version 4 will also have 64 GPR’s instead of 32.

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Robert Finch http://www.finitron.ca


Thu Oct 07, 2021 6:47 am WWW

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1531
Location: Canada
Refined version three by removing the vector register indicator from the target register spec. This indicator is redundant with the exception of two instructions – VEX and V2BITS. If the instruction is a vector instruction then the target register is always a vector register except for the two exceptions aforementioned. Since the bit in the target register spec was wasteful, it has been reassigned. In a similar vein, there are only five instructions where Ra is a scalar register for a vector instruction – VEX, VEINS, VSCAN, VCIDX and BITS2V. Otherwise it does not make sense to have Ra optionally a vector or a scalar register. Since the bit indicating Ra is a vector or scalar register is redundant it has also been reassigned to other uses.

This has led to a major revamping of the instruction set. At the same time the ISA has moved from nybble based addressing to instruction bundles. Seven instructions per bundle. This leads to better use of branch displacements. Speaking of branches, they have been radically altered. They are now compare then branch based as opposed to performing the comparison and the branch at the same time.

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Robert Finch http://www.finitron.ca


Sat Oct 09, 2021 5:15 am WWW
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