DiTBho wrote:
Well, first you have to write the machine-layer for the back-end
So, as a matter of principle, Koy-Emulation I can get at the JavaScript (useful for online browser-level presentation), C (as
VirtualDub-filter) or Python (for Raspberry-Pi).
But C-version (for VirtualDub) or Python (for Raspberry) is very specific cases and nobody need for it.
In this way, the JavaScript online emulation demos I looking as best for first time!
DiTBho wrote:
From the above, I deduce (my pure speculation) that supporting llvm must not as easy as it sounds

Hmmm…
I'm look, for homebrew project that supports for LLVM and C - is very ambicious for non-commercial?
Well, then I will focus on i8080/z80 and JavaScript emulators. And on Verilog model for FPGA…
So, today I'm looking at this code:
Code:
; KOYAANISQATSI BYTE-CODE / ASSEMBLY ; IA-32 PSEUDO-ANALOGY
1234 C9 CC 15 0F|MOV C9,[BC1+5]
1238 B9 BB 16 0F|MOV B9,[BC1+6]
123C 90 CF|JCF BC9+0 ; JCF [BC1+5] ; JNC WORD PTR [EBX+5]
123E C9 CC 17 0F|MOV C9,[BC1+7]
1242 B9 BB 18 0F|MOV B9,[BC1+8]
1246 90 DF|JDF BC9+0 ; JDF [BC1+7] ; JNZ WORD PTR [EBX+7]
It's monstrous! Whole 10 bytes per one branch!
It's very actual problem of conception.
But, nevertheless, I see no reason to change something. Because basic conception started from homebrew core for homebrew processor.
For example:
Code:
; i8080-A --> A1
; i8080-B --> B1
; i8080-C --> C1
; i8080-D --> B2
; i8080-E --> C2
; i8080-H --> B3
; i8080-L --> C3
; i8080-SP -> B4:C4
; i8080-PSW > A1:A0
; i8080-M --> [B3:C3]
;;;;;;;;;;;;;;;;;;;;;
; i8080 "MOV A,B" (78)
7800 A1 AB 1F |MOV A1,B1
7803 00|HLT
;;;;;;;;;;;;;;;;;;;;;
; i8080 "MOV A,C" (79)
7900 A1 AC 1F |MOV A1,C1
7903 00|HLT
;;;;;;;;;;;;;;;;;;;;;
; i8080 "MOV A,D" (7A)
7A00 A1 AB 2F |MOV A1,B2
7A03 00|HLT
;;;;;;;;;;;;;;;;;;;;;
; i8080 "MOV A,E" (7B)
7B00 A1 AC 2F |MOV A1,C2
7B03 00|HLT
;;;;;;;;;;;;;;;;;;;;;
; i8080 "MOV A,H" (7C)
7C00 A1 AB 3F |MOV A1,B3
7C03 00|HLT
;;;;;;;;;;;;;;;;;;;;;
; i8080 "MOV A,L" (7D)
7D00 A1 AC 3F |MOV A1,C3
7D03 00|HLT
;;;;;;;;;;;;;;;;;;;;;
; i8080 "MOV A,M" (7E)
7E00 A1 AA 30 0F|MOV A1,[BC3+0]
7E04 00|HLT
As You can see, it's simple idea of homebrew WYSIWYG RISC-core for execution any processor code, where guest CPU code sets high byte of address of microprogram. And 256 bytes per one guest-instruction - is too much for any tricks! Yes, it's will very slowly practical, but even i8086-code it can get too.
But this Koyaanisqatsi-CPU, as I understand it now, is not WYSIWYG-RISC, but WYSIWYG-CISC turns out anyway!
It still good for homebrew Any-CPU kit station abundantly.
But as an independent CPU it is very weird…
P.S.: All industry offers us a large choice of any fast processors. But all that have just very esoteric machine code anyway, where without translators we cann't doing something!
In this light, my fix idea was the essence of developing a simple and intuitive coding homebrew WYSIWYG-core. Let it is very slow, but it's very openned at byte-code level!