Going back to more 1968 style computer. Word addressing. Accumulator design rather a register to register design.
Subroutine calls on even bountry, and single word 19 bit addressing. This way I can use CALL theading for threaded code. 8 registers including
the PC.
More inspection of the new oder code, conficts with some other decoding,thus I am back to two word calls and the orignal order code.

Moving clock generation to the ALU card as well. The ALU gets to use the master clock first.
Moving up to 1984, with a 1.5 uS memory cycle time -- ram . A 1977 version 1.8 uS core or ram.
PS: Looking at the chips I have, I may tweek it for 150 ns ram, and add a wait state for IO.