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 Started 6809 core 
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Joined: Sat Feb 02, 2013 9:40 am
Posts: 1484
Location: Canada
Works been started on a 6809 core, hopefully I can create a souped up version with more regs/wider addressing that's backwards compatible.
I'm keeping a repo on GitHub. It's lookig to be around 3,000 lines of verilog.

I' wonder if I can make a pmod with a real 6809 on it for comparison purposes. The pmod would have have to connect the 6809 to an FPGA with a minimum number of I/O's. So I was thinking of trying some sort of serial interface. All the 6809 signals would be serialized to and from the FPGA. It's only a 1MHz part that I've got, so if I run the serial interface at 50 MHz. I should be able to capture all the pins.
I have to interface it to the FPGA with 8 pins or less. Any advice ?

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Robert Finch http://www.finitron.ca


Thu Oct 24, 2013 7:57 am WWW

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1484
Location: Canada
Attached is a rough schematic of what I'm thinking.

The 6809 is surrounded by 74hct299 shift registers. The shift registers controls signals come from a 74hct259 bit addressable latch.
Another '259 drives some of the inputs to the 6809.
This requires about 7 pins to control from the FPGA.

Attachment:
sch6809pmod.jpg


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Robert Finch http://www.finitron.ca


Thu Oct 24, 2013 9:32 am WWW

Joined: Wed Jan 09, 2013 6:54 pm
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How fast do you think you can clock those shift registers? Can you slow down or stop the clock on the 6809 to help out?


Thu Oct 24, 2013 8:04 pm

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1484
Location: Canada
According to the spec sheet the 6809 can be clocked as slow as 100kHz. I'd likely need a clock about 40 to 50 times as fast as the 6809 is running to shift 32 bits and have some settling time for reads the 6809 makes. Ideally I'd run the clock 40 to 50MHz and clock the 6809 at 1MHz. But the parts may not work that well at 50 MHz I need to check the specs. So I'll start at 5 MHz clocking the 6809 at 100 kHz.

There is only a single readback bit to interface to the FPGA, so I think just a 100 ohm resister (or a couple of diodes) in series might work for level translation. The FPGA should be able to output a high enough level for high signals to the 5V logic. I plan on using 74HCT parts.

This concept could be used with other slower speed micros. (8088 6502 Z80 6800,...)

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Robert Finch http://www.finitron.ca


Thu Oct 24, 2013 11:21 pm WWW

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1632
5MHz and 100kHz sounds like a good combination!
I read something recently to the effect that there are 3 rather different regimes: 1-2MHz is easy, 12-16MHz takes care, and 40MHz plus is really rather difficult.
(It was in the comments to http://slashdot.org/story/13/10/18/2340 ... rdware-dev but I don't necessarily recommend reading them all! It did mention "failure of 40MHz VL-bus. There's a reason why the industry took a step backwards to 33MHz for PCI, and so many budget motherboards had only 2 or 3 slots")
Cheers
Ed


Fri Oct 25, 2013 10:50 am

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1484
Location: Canada
I'm stumped at the moment. I've tried to get the 6809 core working in an FPGA system. It's outputting the previous instruction as an address, rather than the address field of the current instruction. (I dumped it to the LEDs on the FPGA board). The strange thing is that it works fine in simulation and I can't find what's causing the difference.

For the 6809 interface I got rid of the 's259 parts off the schematic as they'd probably be too slow for what I want. It's an eight wire interface with most signals direct to/from the FPGA.
Attachment:
interface6809.gif


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Robert Finch http://www.finitron.ca


Wed Oct 30, 2013 6:07 am WWW
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Quote:
I've tried to get the 6809 core working in an FPGA system. It's outputting the previous instruction as an address, rather than the address field of the current instruction. (I dumped it to the LEDs on the FPGA board).

Any chance the mechanism that dumps the info to the LEDs is faulty? In a perplexing troubleshooting situation, one must remember to mistrust the instrumentation! Just a reminder -- I'm sure you know that already.

Re- your board with the actual 6809E: That '164 shift reg kinda had me puzzled but I guess you're only using 1 of its 8 stages. It accepts QCLK as its serial input and the very first stage's output goes to the CPU "E" input?

Also, I take it this board isn't involved in the present investigation -- instead you're just comparing the simulation of the core with the FPGA rendition...?

-- Jeff

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http://LaughtonElectronics.com


Sat Nov 02, 2013 12:06 am WWW

Joined: Sat Feb 02, 2013 9:40 am
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Location: Canada
Quote:
Re- your board with the actual 6809E: That '164 shift reg kinda had me puzzled but I guess you're only using 1 of its 8 stages. It accepts QCLK as its serial input and the very first stage's output goes to the CPU "E" input?


The '164 delays the Q signal by 8 clock cycles (as much as can be done with a single shift register). The CLK signal is a 64x Q clock so E doesn't work out to be 25%(quadrature) delayed (It's only 1/8 12.5% delayed). But it's slow enough that it meets the timing requirements, and should hopefully work with a CLK up to 40MHz. I use the '164 in order to save an I/O pin from the E CLK otherwise I'd need another !/O.

I managed to get the 6809 core working past the LED thing. I still don't know how I did it, but it works now. It's now lighting up LEDs as status indicators. I hope to have the core displaying a message on-screen soon.

'HCT299 parts just arrived today. I bought them off ebay. Now to start wire-wrapping.

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Robert Finch http://www.finitron.ca


Sat Nov 02, 2013 2:11 am WWW

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1484
Location: Canada
It clears the screen ! That indicates large parts of the core are working. Subroutine call/return pushing / popping parameters, branching etc. The guts of clearscreen routine listed below. ScreenLocation holds a 32 bit pointer to the text screen. Far indirect mode works like the 6502 indirect addressing.

Code:
0000F1AA 108E0000                ldy             #0
                      cs1
 0000F1AE 151BEDB90010            std             far [ScreenLocation],y  ; clear the memory (far outer indexed indrect)
 0000F1B4 3122                    leay    2,y                                     ; increment y
 0000F1B6 301F                    leax    -1,x                            ; decrement x
 0000F1B8 26F4                    bne             cs1

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Robert Finch http://www.finitron.ca


Sat Nov 02, 2013 3:45 am WWW
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