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 TTL 48 bit cpu 
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Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
The DE-1 FPGA now emulates a 48 bit cpu, using a 16 bit bus. Needed to add a new instruction SC6, to scale
a number by 6, for indexing 48 bit numbers. Data sizes are byte (unsigned 8 bits), short (16 bits), long (48 bits).
No RISC here, as a 1973 memory cycle takes ~ 800 ns. Byte Prime number sive ~ 15 seconds.
The order code is the same as the 8/16/32 bit cpu. Floating point needs to be revised still, but the bios roms
are updated with the new format.
Some tweeking is still needed, and off to make a back up before some thing BAD hap$%#!


Thu Mar 09, 2023 5:45 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
With the wider word length, I have added excess 3 code back in. Now I have the option for 10 digit BCD floating point,
Ben.


Fri Mar 10, 2023 8:51 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619

Marty: Flux capacitor?
Dr. Brown: It's taken me almost 30 years and my entire family fortune to realize the vision of that day. My god, has it been that long?

I have compleated a prototype design I am happy with, for a binary computer with a 16 bit data bus.
The 48 bit binary floating point routines are now in rom, (38 bit mantissa+sign+9 bit binary exponent.)
Memory is 1 Meg ram Max with 64Kb user space and 32kb kernal space as standard for 1973..1975
.
This a mid-sized single user computer, because I have no good knowlage on how to write a os
with a simple mmu Minix fails because it is too tied to the PC and the 8086/8088. A two small fixed discs
of 1.5 mb is standard as well, with a seral port (2400 baud) and glass tty console.(80x24)

The major reason to go to 48 bits was to have a sane software floating package ~ 11 digits.
32 bit floating point 6? digits.
You may be able have a spread sheet, for the home on a Apple II but not for much more.

Ben.


.


Thu Mar 16, 2023 12:20 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Now Algol ready, with EQV and 4 more BASE registers.
Looks again at how complex ALGOL 68, maybe it is not ready at all.
Ben.


Fri Mar 17, 2023 8:11 am

Joined: Sun Oct 14, 2018 5:05 pm
Posts: 62
oldben wrote:
Now Algol ready, with EQV and 4 more BASE registers.
Looks again at how complex ALGOL 68, maybe it is not ready at all.
Ben.


Think I might start with a good macro assembler ...

But sounds good so-far.

-Gordon


Fri Mar 17, 2023 10:28 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Full Algol can use threads and coroutines and have strange nested variables and pointers and dynamic sized strings and arrrays.
This requires a complex procedure stack frame, that requires a memory pool function rather than simple stack. That is why it took
10+ years to define the langauge and 10+ years for a compiler to be witten. I just picked the book 'the run-time structure of a algol 68 student check out compiler , fall 1976' (reprint from India).

I need a good memory pool routines, that can move the heap around, and some way of reflecting pointers have moved
around. It is out there, finding it is hard as every thing C based. Once that is done then I can get back to software.
It looks like I need to have flags bits in my pointer varables , a marked bit, dirty bit, null bit at least, and way to not update
the flags on alu operations.
Ben.


Fri Mar 17, 2023 6:34 pm

Joined: Sun Oct 14, 2018 5:05 pm
Posts: 62
oldben wrote:
Full Algol can use threads and coroutines and have strange nested variables and pointers and dynamic sized strings and arrrays.
This requires a complex procedure stack frame, that requires a memory pool function rather than simple stack. That is why it took
10+ years to define the langauge and 10+ years for a compiler to be witten. I just picked the book 'the run-time structure of a algol 68 student check out compiler , fall 1976' (reprint from India).


Were there any properly successful Algol68 implementations?

Coroutines are nice - can be emulated in any old BCPL/B/C program, but giving each routine its own stack can be handy. Threads - I implemented a form of threading in my RubyOS - actually directly inside the Cintcode VM. It's strict round robin (for now) and a thread can run for up to 10ms then the next one takes over at the next 'critical' instruction inside the VM. Threads can voluntarily give-up the rest of their time-slot so they'd just typically sit in a loop until the grim reaper comes along...

oldben wrote:
I need a good memory pool routines, that can move the heap around, and some way of reflecting pointers have moved
around. It is out there, finding it is hard as every thing C based. Once that is done then I can get back to software.
It looks like I need to have flags bits in my pointer varables , a marked bit, dirty bit, null bit at least, and way to not update
the flags on alu operations.
Ben.


Not sure why, but I am reminded of this:

http://www.catb.org/~esr//jargon/html/k ... #id3141202


and while I admire your dedication, I do wonder about the task ahead. I'm not convinced implementing Algol (of any year) is sensible - especially when other things might be easier. FORTRAN? Or - Coral 66? apparently there is source code available - in BCPL... Edinburgh Imp (Imp77) ?

But then again, I never thought I'd write an OS in BCPL - however the advantage I had/have is that the compiler was already written for me and all I had to do was sacrifice some braincells to the 65816...

-Gordon


Fri Mar 17, 2023 7:14 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
The Newest improvement Make it slower, Made the instruction pointer P, now a general purpose register.
The only special instruction is now JSV ( jump and save on the stack), other than branches. This frees me two
opcode slots for something new. Ben.


Sat Mar 18, 2023 2:56 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
I need to revise the order code layout to make all fit. Added a swap a (r) instruction. Forth and other Zero operand code most likely
will be subroutine threaded, but not sure of the details yet. Ben.


Sat Mar 18, 2023 7:28 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
I will by trying out a few ideas, that may or may not work with the FPGA, but the general lay out is done for the instructions.
Most work now will be software rather than hardware. I need to get back to the meta II compiler compiler and add symbol table.
I may give Small C a try again. Ben.


Sun Mar 19, 2023 1:56 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Found a few bugs. One was using 'A' - '9' as constant, but my assembler does not support that feature.

Added in a simple MMU. Using A20 as mmu flag, 0 use map+address, 1 direct address.
512Kb is max segment size, the same as the max memory on the FPGA card. The MMU and IRQ service
are reseved for later use.
64Kb user space and 32Kb kernel space, looks to be able space for the assembler
and what ever compiled languages I use.
I will get back to the meta compiler, once I design a language. I am thinking of having
spaces ignored so longer names make sense.
Code:
if  does it have 4 legs , then I am a cow = true ,

rather than DoesItHave4Legs. The first compiler will translate to C to I can re-write my cross assembler
and cross compiler in native code.


Fri Mar 24, 2023 3:26 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Tried to get a 64 bit cpu working, but no luck so far. I can get 'hello world' programs working'
but for some reason the disc i/o routines are not working. For now a 48 bit machine is a big as they
get. Ben.


Sat Apr 15, 2023 1:20 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Removed byte imediate -128+127 for quick immediate -8+7. This lets me have 7 more GP registers.
The default is A B C D I J K W X Y S and PC. E F G H can be added later.
A lite 32 bit cpu is in the works. I hope I have ample default registers for 64 bit floating point.
A bitslice/74Fxx design looks to clock at 12 Mhz. 8 mhz for the standard (fpga) version.
Ben.


Thu Apr 20, 2023 4:25 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Finished the 32 bit cpu. Using 2901A's (bitslice) and 82S100's (PAL) ,ball park timing gives me ~ 400 ns timing depending on
the PROM speeds. Main memory is16k drams @ 150 ns (1979). A 18.432 Mhz osc is used for the Uart clock and 1/2 that for the master clock, .434 us memory cycle.The FPGA has a .440 us memory cycle using a 25 mhz clock.
Using a 24.54 Mhz clock, it is .450 us.
Having problems with the build using the video terminal, I may strip that out and just use serial I/O.
Ben.


Fri Apr 21, 2023 7:44 am

Joined: Sun Oct 14, 2018 5:05 pm
Posts: 62
oldben wrote:
Finished the 32 bit cpu. Using 2901A's (bitslice) and 82S100's (PAL) ,ball park timing gives me ~ 400 ns timing depending on
the PROM speeds. Main memory is16k drams @ 150 ns (1979). A 18.432 Mhz osc is used for the Uart clock and 1/2 that for the master clock, .434 us memory cycle.The FPGA has a .440 us memory cycle using a 25 mhz clock.
Using a 24.54 Mhz clock, it is .450 us.
Having problems with the build using the video terminal, I may strip that out and just use serial I/O.
Ben.


Good news!

Now you can implement BCPL ;-)

Cheers,

-Gordon


Fri Apr 21, 2023 9:39 am
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