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 TTL 48 bit cpu 
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Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
drogon wrote:

Good news!

Now you can implement BCPL ;-)


Cheers,

-Gordon


That might be true. I just can't figure out how to write programs yet.
All the ($ and $) as well as the ! 's get me confused.

I just spent all night and all my cash shopping for a good used $500.00 terminal.
That the problem with retro, you need a small terminal for todays projects.

I spent another $75 on a mini cyclone II development system. This way I can fake a
micro-processer chip rather than a bit slice cpu. Ram and cpu on one card,
I/O on the other cards. Not sure of the clock speed, but ROM will be slow compared to the
inner speed of the FPGA. At least IBM AT speed.
Ben.


Fri Apr 21, 2023 1:52 pm

Joined: Sun Oct 14, 2018 5:05 pm
Posts: 62
oldben wrote:
drogon wrote:

Good news!

Now you can implement BCPL ;-)


Cheers,

-Gordon


That might be true. I just can't figure out how to write programs yet.
All the ($ and $) as well as the ! 's get me confused.


Well... ($ and $) have been deprecated for a few decades now and ! is just a short-cut for array []'s, so hello world in BCPL is:

Code:
GET "libhdr.h"

LET start () = VALOF
{
  writes ("Hello, world!*n")
  RESULTIS 0
}

AND sum (array, elements) = VALOF
{
  LET sum = 0
  FOR i = 0 TO elements-1 DO
    sum := sum + array!i
  RESULTIS sum
}


So not much different from C, really...

(There is a += style operator in modern BCPL, but it looks like
Code:
sum +:= array!i
which I'm not fond of...

My 32-bit RISC-V bytecode VM for BCPL is about 10KB of object code (could be much less if I didn't have many macros which are expanded for speed) and uses about 11 of it's 32-bit registers with all the VM/Bytecode state being held in registers, however if you have less registers then RAM can be used...

Quote:
I just spent all night and all my cash shopping for a good used $500.00 terminal.
That the problem with retro, you need a small terminal for todays projects.


Or a computer running a good terminal program - I've used minicom under Linux for a long time now. Advantage over a real terminal is that you can copy & paste in/out of it relatively easily and things like minicom support xyz modem, etc. ...

Quote:
I spent another $75 on a mini cyclone II development system. This way I can fake a
micro-processer chip rather than a bit slice cpu. Ram and cpu on one card,
I/O on the other cards. Not sure of the clock speed, but ROM will be slow compared to the
inner speed of the FPGA. At least IBM AT speed.
Ben.


I figure money spent on making life easier is money well spent...

And FWIW: My 1979 32-bit system was the Interdata 7/32 - the system I used had 256K of core (although I'm not sure if that was bytes or words) and ran a home-grown (from Edinburgh uni) multi-user OS that supported about 8 users and a batch system and was programmed in yet another algol like language; Imp77... I have more than once thought about writing an emulator for it (even though there is a SIMH one), but life keeps getting in the way..

So anythings possible...

-Gordon


Fri Apr 21, 2023 3:23 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
I say you need to get that Interdata running again. Think how many users you can run online, from the net. :)
Even a simh emulation would be nice, so people could see what ran for time sharing before the pc, and UNIX.
Ben.


Fri Apr 21, 2023 6:06 pm
User avatar

Joined: Sun Dec 19, 2021 1:36 pm
Posts: 78
Location: Michigan USA
Quote:
I just spent all night and all my cash shopping for a good used $500.00 terminal.
That the problem with retro, you need a small terminal for todays projects.


I'd be interested to see some photos or a description of what you are planning to go with for a terminal. Thanks!


Fri Apr 21, 2023 9:26 pm WWW

Joined: Sun Oct 14, 2018 5:05 pm
Posts: 62
oldben wrote:
I say you need to get that Interdata running again. Think how many users you can run online, from the net. :)
Even a simh emulation would be nice, so people could see what ran for time sharing before the pc, and UNIX.
Ben.


We already have Unix in'79- my first experience was in 1980 on a PDP11/40 running Unix v6 ...

The Interdata thing was a sort of spin-off from the main Edinburgh University project - a multi-user/tasking OS called EMAS - The Edinburgh Multi-Access System. Much has been written (and lost) about it. Some information here:

http://www.bobeager.uk/emas/index.html

The Interdata system was an OS called Mouses.

If I had time I'd like to try to get back into it - it was my first real introduction to a time sharing system, structured programming (in Imp77) and many other things fascinating for a 16/17 year old back then...

EMAS is one of those "could have been" .. things, but history is, as always, written by the winners. Maybe if it had originated in Cambridge (MA or England) rather than Edinburgh then who knows.... But I guess we never will.

-Gordon


Fri Apr 21, 2023 9:36 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Quote:
EMAS is one of those "could have been" .. things, but history is, as always, written by the winners. Maybe if it had originated in Cambridge (MA or England) rather than Edinburgh then who knows.... But I guess we never will.

I think the problem is the model, All this knowlage and software is property of the State, the public never sees it.
AT&T permited public source access for Unix.
Microsoft and Apple sold software, so the public could access it, thus the winner,
Ben.


Sat Apr 22, 2023 6:21 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1789
Thanks for the EMAS note, Gordon, posted over at retrocomputingforum.

Ben, I have no idea what your thinking is, but it seems to be very unclear. At least one person believes you are deliberately provocative.


Sun Apr 23, 2023 8:07 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
I am retireing the the 48 bit cpu and revising the the 32 bit one to have a small 8 bit I/O bus.
This will have a few serial ports and a IDE compact flash drive. The sd card, video terminal
and serial I/O was just too much of a hack to get around problems with internal fpga routing problems.
Today I plan to clean up hardware bus I/o and software disk routines, to have a more standard interface
assuming the FPGA routes it correctly.
Ben.


Sun Apr 23, 2023 9:01 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
It looks like the FPGA can handle the mini-port for two uarts, and a IDE drive. Clock speed will be ~ 5.5 mhz
~ .725 us around 1979. Before that the clock speed was 4 mhz (1.00 us) with 4K drams. Now just to wait for the parts.
Ben.


Wed Apr 26, 2023 7:40 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Dropped the speed to 4.9 Mhz and 1200 baud. I have the IDE,compact flash parts in, so all I needed to do is to draw the schematic
and wire up the cable, and write software.
Ben.


Sat Apr 29, 2023 6:54 pm

Joined: Sun Oct 14, 2018 5:05 pm
Posts: 62
oldben wrote:
Dropped the speed to 4.9 Mhz and 1200 baud. I have the IDE,compact flash parts in, so all I needed to do is to draw the schematic
and wire up the cable, and write software.
Ben.


Hope it works!

-Gordon


Sun Apr 30, 2023 4:33 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Attachment:
card_.jpg
I got looking at the prototype boards I got, I may be able to get the front panel done on the same sized card.
If I revise the cpu just to boot from rom, and use GAL's I may be able to prototype on the same sized cards
as well.


You do not have the required permissions to view the files attached to this post.


Fri May 05, 2023 8:49 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
4 - 40 pin 4 bit 2901's don't fit, so I need to order some 29C101's; a 16 bit bit slice in a 64 pin package.
A mix of 16v8's and 22v10's will form the data path.
A new format of microcode will be used, since the front panel
is removed from this design.
The roms (27C64's) will be buffered by pal's as a D latches, that could do minor input logic like reset.
Clock speed of 5.5 Mhz is possible at least, perhaps 7.3 Mhz will work as well.
Further design will follow after I get the current projects built.
Ben.


Sat May 06, 2023 8:57 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Ballpark figues for breadboarding , 11 chips for the ALU, 14 or 15 chips for Control logic depending if I have front panel.


Tue May 09, 2023 7:26 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 619
Ordered another set of 2 CY7C9101s. This way I am ample for a 48 bit CPU, or 2 32 bit ones.
Clock speed 6.144 mhz, about right for 2901A's. Using all PALs it looks like can get all to fit on the protoype
breadboards. Using more modern chips, for faster I/O. The uarts,RTC,and FLASH CARDs are still simple i/o.

Ben.


Thu May 11, 2023 8:19 pm
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