Last visit was: Sat Jul 31, 2021 4:47 am
It is currently Sat Jul 31, 2021 4:47 am



 [ 7 posts ] 
 Early HP Calculator Technology 
Author Message

Joined: Mon Aug 14, 2017 8:23 am
Posts: 156
This is a follow-on from my late 1960s calculator discussion.

It covers the progression from discrete transistor technology, through SSI, MSI and ultimately LSI devices - specifically those used by Hewlett Packard in the very early 1970s.

HP had released a transistor based programmable, scientific desktop calculator back in 1968 the HP9100A.

The HP 9100A is well documented in the September 1968 issue of the HP Journal

http://hparchive.com/Journals/HPJ-1968-09.pdf

Whilst other manufacturers were engaged in producing basic 4 function calculators, HP focussed on a different market, a machine that could be used for scientific and engineering calculations.

The HP 9100A was the first scientific calculator, in modern parlance, capable of calculating trigonometric, logarithmic and exponential functions, and in calculator terms it was fast performing an add in 2mS and a Sin, Cos or Tan in 280mS.

The HP 9100A was a very expensive desktop machine, around $5000 in 1968, when a PDP-8 sold for less than $20,000.

It used Reverse Polish Notation (RPN) and was a stack based machine.

Wikipedia covers it here: https://en.wikipedia.org/wiki/Hewlett-Packard_9100A

Bill Hewlett was inspired by the 9100A project and challenged the engineers to come up with a 9100A equivalent that fitted into an engineer's shirt pocket.

http://codex99.com/design/the-hp35.html

This challenge had to wait until November 1970, when LSI had progressed to the point where a cpu could fit onto a chip or two, and low voltage logic and small ROMs were becoming commercially available.

The lead engineer, Dave Cochran from HP contacted Fairchild to discuss modifying one of their 4 function chip sets, but Fairchild were not interested. However Fairchild put them in contact with their customer, Sweda - the cash register company, and it was this Sweda bit serial design that formed the original basis of the HP pocket calculator series.

After cpu modifications were simulated by computer (an HP first) the modified logic design was passed over to Mostek for implementation in MOS as a two chip set: Arithmetic and Registers and Control and Timing. The mask programmed ROMs were handled separately by AMI.

The cpu was a bit serial design, specifically designed to handle floating point BCD arithmetic. It was a Harvard architecture receiving 10-bit wide instructions from ROM. Internally it worked with 56 bit wide registers (14 digits) which included 10 digit mantissa, 2 digit exponent and a digit for each of the mantissa sign and the exponent sign.

Internally there were 7, 56 bit wide registers, A and B were general purpose, C held the results to display and a 4 level push down stack was formed from 4 registers X,Y, Z and T.

Not all register to register moves were implemented, for simplicity, only certain permutations were possible.

The HP 35 program was contained in three, 256 x 10-bit ROMs. These were addressed serially using an 8-bit serial address bus. This was similar to page addressing, and extra logic was required to "page-select" which ROM was currently being addressed. This scheme allowed for up to 8 ROMs (or RAMs) to be addressed.

Later calculator models would retain the same processor, keyboard and display circuitry, but would be customised for various market functions by changing the number and contents of the ROM. Eventually a 1024 x 10-bit ROM became available, but it still retained the same basic ROM addressing structure. Sending only 8 serial bits to address a ROM is faster than sending a full 10 or 11 bits.

Not only were ROMs addressed on a serial address bus, but the 10-bit data was returned on a serial instruction bus. The HP 35 was clocked at 200KHz (800kHz divided by 4 to produce a 2 phase clock and internal timing signals) but this was sufficiently fast that all trig, log or exponential functions could be calculated in under 500mS. Whilst this serial addressing and arithmetic would be slow by contemporary minicomputer standards, it was sufficient for the calculator application.

The internal serial bus was created to keep inter-chip signals to a minimum. The HP engineers envisioned a series of peripherals, such as printer or card reader that could also be connected to the cpu using the serial bus. This serial bus is effectively an early cousin of the now-ubiquitous SPI serial communications standard.

The HP 35 and it's successors became popular with engineers and this has led to an interest in the reverse engineering and simulation of its workings. ROMs have been de-capped and their contents explored using examination under the microscope.

A lot of details of the trig functions and reverse engineering of the HP 35 operation can be found here:

http://home.citycable.ch/pierrefleur/Ja ... 20Saga.htm

So far, I have not found any specific data on the HP 35 cpu, but as it was used across a range of calculators, it crops up in an early patent (filed in 1972) for a business calculator.

Fortunately there is significant detail in this patent, including block schematics, timing charts, instruction sets and even a ROM dump.

This patent (US 3863060) can be found on Google Patents here

https://patents.google.com/patent/US3863060A/en

and as an easier pdf here: https://www.keesvandersanden.nl/calcula ... 863060.pdf


Last edited by monsonite on Thu Feb 25, 2021 12:24 pm, edited 2 times in total.



Wed Feb 24, 2021 3:27 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1626
.
Nice thread! Have you seen Peter Monta's work?


Wed Feb 24, 2021 5:10 pm

Joined: Mon Aug 14, 2017 8:23 am
Posts: 156
BigEd wrote:
.
Nice thread! Have you seen Peter Monta's work?


Yes, Ed,

I spotted that earlier this morning. Amazing that you can use a microscope/photomicrographs to "read" the ROM contents from ROMs of that era.

There is a wealth of HP-35 (and later models) information but I am yet to find some more on the cpu chips used.

The patent US 3863060 provided the best description of the instruction set and there are more than one emulations of the HP 35 online, including a couple for the Arduino.

http://home.citycable.ch/pierrefleur/Ja ... rduino.htm

This was a specialised cpu intended for floating point BCD arithmetic, developed at a time when ROM was an extremely precious resource. It's quite amazing that they managed to cram so much into just 768, 10-bit words.

In contrast, when general purpose cpus (6502, Z80 etc) became available a few years later, significant advances had been made to both ROM and RAM technology, allowing much larger resources.

Some interesting points from the patent.

As the ROM instructions were shifted serially into the instruction decoder, the first two lower bits were coded to represent a jump or a conditional branch. The branch target address was encoded into the following 8 bits. This allowed the instruction decoder to have prior warning of a branch, and set up the cpu accordingly - before the target address was even finished loading.

The upper 3 bits of the instruction were used (in certain modes) to define the page address of the "long branch". These 3 bits were decoded to select which of the 8 possible 256 word ROMs was to be selected next. These bits could be quickly decoded without tying up further cpu resources.

Each key when pressed generated a keycode. This was used directly as a jump address into the ROM from where another address of the key-handling function routine would be executed. This provides a very efficient way of calling the various function routines - such as sin, cos, tan etc...

Later, when the engineers were thinking about a programmable version of the calculator, the keycodes (in octal) were used as the shorthand codes for each of the programming steps. A 2 digit octal number is 6 bits, but once decoded this could provide a jump address of an 11 bit addressing range. This is described in this patent:

https://www.keesvandersanden.nl/calcula ... 855461.pdf

The HP-35 had no external storage, only the 7 internal registers. RAM was added later when the first programmable calculator of this series, the HP-65 appeared in 1974.

https://en.wikipedia.org/wiki/HP-65

As there appears to be a shortage of original technical documentation - after all the cpu was HP proprietary and probably a closely guarded secret, the best information appears to come from the various HP patents. This site summarises these for easy reference:

https://www.keesvandersanden.nl/calculators/patents.php


Wed Feb 24, 2021 6:11 pm

Joined: Mon Aug 14, 2017 8:23 am
Posts: 156
Tom Osborne developed the "Green Machine" that ultimately became the HP 9100A.

Tom went on to work on the HP-35 and the programmable HP-65.

Here's a 1994 article describing his part in the projects:

http://www.hp9825.com/html/osborne_s_story.html


Wed Feb 24, 2021 6:58 pm

Joined: Mon Aug 14, 2017 8:23 am
Posts: 156
The HP-35 featured in the June 1972 edition of the HP Journal

http://hparchive.com/Journals/HPJ-1972-06.pdf

Good information if you want a broader idea of how engineering calculations ( previously on a slide rule) were revolutionised by the HP-35.


Thu Feb 25, 2021 12:49 am

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1626
Ashley Feniello's work here is worth a look:


Thu Feb 25, 2021 1:31 am

Joined: Mon Aug 14, 2017 8:23 am
Posts: 156
I have been looking at Ken Schiriff's reverse engineering of the Sinclair Scientific Calculator - from about 1974.

http://files.righto.com/calculator/sinc ... lator.html

This document is well known amongst the hacker community, as Clive Sinclair's calculator development team (mostly Nigel Searle) pulled off a major hack on a TI calculator chip, converting a basic 4 function calculator to a scientific calculator - capable of trig, log and exponential function calculations.

The calculator chip in question was a TMS0800 series device, normally intended for the 4 function calculator market.

However, when you compare the TMS0800 to the HP-35 chipset, there was not a huge amount of difference between them. The TI part being later to market, and thus having a greater level of integration had an onchip ROM and all control and timing included on the same device.

The TI had three 44 bit registers whilst the HP had seven 56 bit registers. As these were arranged as 4 bit BCD digits, with mantissa, exponent and 2 sign digits - it is the difference between a 12 bit mantissa and a 10 bit mantissa

The TI had 320 words of 11-bit ROM, whilst the HP-35 had 768 words of 10-bit ROM.

Both processors were capable of addition, subtraction, comparison, shifting, incrementing and decrementing. Unlike a general purpose cpu - there was no AND, OR, XOR instructions.

Each processor was tailored to the requirements of floating point BCD math. This meant that a register contents could be selected on a field by field basis. The field might be the mantissa, mantissa sign, exponent, exponent sign, the whole word or any of the individual digits. This gave great flexibility when it came to operating on the registers.

Sinclair managed to shoehorn the scientific functions into the 320 words of ROM. He had to take shortcuts and this meant that the accuracy of some functions was only about 3 decimal places.

If he had had the luxury of a bigger external ROM (like the HP) he would probably have been able to make the TI part perform with greater precision.

The design of the TI device is well covered in this US patent:

https://www.pat2pdf.org/patents/pat3934233.pdf


Thu Feb 25, 2021 7:15 pm
 [ 7 posts ] 

Who is online

Users browsing this forum: CCBot and 0 guests


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Jump to:  
Powered by phpBB® Forum Software © phpBB Group
Designed by ST Software