Tomasulo + Reorder Buffer = Interruptible Out-of-Order
ENEE 446: Digital Computer Design, Fall 2000
Prof. Bruce Jacob, http://www.ece.umd.edu/~blj/

This paper describes an out-of-order implementation of the 16-bit Ridiculously Simple Computer (RiSC-16), a teaching ISA that is based on the Little Computer (LC-896) developed by Peter Chen at the University of Michigan.

This page includes documentation on the instruction set and several different processor implementations, including sequential, pipelined, and out-of-order. Verilog for the out-of-order core is also available for download. Verilog for the other implementations is not available, because those are projects that I assign to my architecture students.