My thought was to use the RiSC-16 ISA as the starting point: https://user.eng.umd.edu/~blj/RiSC/RiSC-isa.pdf

The goal is forward source compatibility with RiSC-16, but not complete binary compatibility due to the extensions.

This ISA only allows eight instructions, so these instructions are exactly the same as their RiSC-16 equivalents: LW, LUI, SW, ADDI, BEQ, and JALR. Missing are ADD and NAND which I think could be replaced by a single instruction.

The ALU RRR-type instructions have bits 3, 4, 5, and 6 defined to be zero, but that opens up an expansion opportunity. Like the PDP-8's OPR instruction you embed additional CPU control signals into the instruction. This allows you to replace the ADD instruction with the ALU instruction which uses the RiSC-16 ADD instruction format, but the four unused bits are used to encode the ALU operation. Two are required for the base ISA: ADD and NAND. If you use %0000 for ADD that instruction is bitwise identical to the RiSC-16 ADD instruction. The value %0001 could be used for NAND which completes the original RiSC-16 instruction set.

That also leaves fourteen additional ALU operations which could be encoded as the ALU is extended with new functions. Some candidates: ADDC, SUB, SUBC, AND, OR, XOR, ASL, LSR, ROL, ROR, and XCH (swaps high and low bytes). I know some RISC architectures don't have carry flags, but ARM does, so it's not unheard of.

There's also an unused opcode %010 which was formerly the NAND instruction that could be used for a new instruction.

My thinking is that Bruce Jacobs and Peter Chen probably know more about designing an ISA than I do. Also, there are existing implementations of RiSC-16 that could be used as a reference architecture. So this would be a better starting point.

Hi Martin,

If you do get going on this project certainly post the designs/circuits you come up with, I printed out all the PDF's in that series (https://user.eng.umd.edu/~blj/RiSC/) some time ago and tried to envisage how the decoding pipeline would work in TTL logic. keen to see what you build (no pressure )

I'll definitely start a hardware thread if I start design and construction. I have a VGA project for my 65816 machine on deck first.

The only CPU I've designed was in the NAND game https://www.nandgame.com/, but I learned a ton while playing it. I've also watched videos on Dr Matt Regan's YouTube channel: https://www.youtube.com/@DrMattRegan.

My thinking is that the first draft of the ALU is the place to start. It's D flip flops to buffer the A and B inputs, four adder IC's, NAND gates, and two input multiplexers to select the ALU function. Another approach is using some 74181's that I have. In either case that seems like a doable first piece of the project.

The register file is the next component, Unfortunately, register file chips like the 74LS172 are obsolete and scarce. I've seen them on eBay for $4.00 each plus $15 shipping. Which means I would need to build a register file using either a 3 to 8 decoder and some D flip flop chips, or an SRAM. Either approach makes the sequencer more complicated because you can't drive both the A and B inputs of an ALU at the same time as a 74LS172 can.

The sequencer would be two EEPROMs to create a state machine with the appropriate control lines for each state, and the state transitions. No need for counter IC's as you encode the next state in the microcode itself. Dr Matt Reagan uses this technique for most of the machines he builds.