ZENTEC MICRODEVICES

                 Zg/α600 Microprocessor Abstract (Prototype)

                       Jan Augustyn & Stanisław Nowak

                          28.I.1971 — Draft: Δ00


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INTRODUCTION
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⟪Preface,Introductory Notes⟫


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ARCHITECTURE
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Register Set
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    [A]  : Accumulator            6-bit
    [X]  : high address/page      6-bit
    [Y]  : low address/index      6-bit
    [XY] : index register-pair   12-bit
    [PC] : program counter       12-bit
    [F]  : processor status       6-bit
    [SC] : stack counter          3-bit

The register set of the Zg/α600 is intentionally minimal and consists entirely
of special-purpose registers. This choice was driven by the need to provide the
essential functions for embedded control at the smallest practical cost: an
accumulator for arithmetic and logic, a pair of index registers for efficient
memory access, a program counter, a status register, and a counter for the
internal stack. The resulting architecture trades some programming flexibility
for a compact instruction set well suited to the industrial and hobbyist
applications targeted by the processor.


    **Accumulator
        The accumulator, A, is 6-bit and is the central working register of the Zg/α600
        and the sole destination for every arithmetic and logical operation. All
        two-operand instructions use the A register as their implicit first operand,
        combining it with a second operand supplied by an immediate value, an absolute
        memory location, or an indirect memory location. Single-operand operations act
        on A exclusively; there is no equivalent form that operates on the index
        registers or on memory directly.
       
        Every instruction that writes a new value into A generates the Zero and Negative
        flags from that value, and does so identically whether the value originated from
        an arithmetic operation or from memory. The Carry and Overflow flags apply only
        to arithmetic operations; see ⟪Status Flags⟫ for details.
       
        The compare operation is a notable exception among instructions that reference
        A: it reads the accumulator and updates flags according to the comparison, but
        never modifies the contents of A itself.
       
        The accumulator communicates with memory exclusively through load and store
        operations; there is no other path by which A exchanges data with the address
        space. On reset, A is cleared to zero; see ⟪Reset/Power-on⟫ for details.

    **Index Register-pair
        The index registers, X and Y, are each 6-bit and are hardwired to form the
        12-bit index register-pair XY, with X always occupying the high half {11:6} and
        Y always occupying the low half {5:0}. This pairing is fixed and is not
        configurable; it exists specifically to supply the effective address used by the
        register-indirect addressing mode. The pair is formed by direct concatenation,
        with no offset or arithmetic applied between the two halves.
       
        X and Y may be loaded, stored, and transferred into individually, or loaded
        together as the full 12-bit pair. None of these operations affect any processor
        status flag, regardless of whether they target a single half or the full pair.
       
        Increment and decrement operate only on the pair as a whole; there is no
        provision for incrementing or decrementing X or Y independently. Increment and
        decrement treat XY as a single 12-bit value, with a carry or borrow propagating
        from Y's top bit into X as needed. Overflow and underflow of the 12-bit pair are
        not detected or flagged; the value silently wraps and no processor status flag
        is affected by this operation.
       
        The index registers support no operation that reads their contents without
        modifying them; there is no compare or test form analogous to what is available
        for the accumulator. On reset, both X and Y are cleared to zero; see
        ⟪Reset/Power-on⟫ for details.

    **Program Counter
        The program counter, PC, is 12-bit and holds the address of the next
        instruction. PC advances by a fixed amount after each fetch, determined by
        instruction class: one word for Class 0 and Class 3, two words for Class 1, and
        three words for Class 2.
       
        On reset, PC is loaded with the fixed address @0000. Placing the reset address
        at the base of the address space allows a small boot ROM occupying the lowest
        addresses to run first and initialize peripherals before handing off to the
        remainder of the program. See ⟪Reset/Power-on⟫ for details.

    **Processor Status
        The processor status register, F, is 6-bit and holds five condition flags:
        Carry, Zero, Negative, Overflow, and Interrupt (mask), along with one reserved
        bit. F has no direct load, store, or transfer form; its contents are modified
        only as a side effect of flag-setting instructions, the explicit interrupt-mask
        instructions, and the stack save/restore that occurs on subroutine calls,
        interrupts, and return. Refer to ⟪Status Flags⟫ for bit-level positions and the
        detailed behavior of each flag, including the reserved bit.
       
        On reset, the whole of F is cleared; see ⟪Reset/Power-on⟫ for details.

    **Stack Counter
        The internal stack counter, SC, is 3-bit and holds the location of the next
        available 18-bit layer in the eight-entry hardware stack, incrementing after a
        push and decrementing before a pull. There is no direct load, store, or transfer
        form for SC; it is moved only implicitly, as a side effect of the push and pull
        operations performed during subroutine calls, interrupts, and return.
       
        SC has no overflow or underflow detection. Should a push or pull wrap the
        counter past its bounds, no warning is raised and the condition is treated
        strictly as a programmer error. On reset, SC is cleared to zero; see
        ⟪Reset/Power-on⟫ for details.


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Status Flags
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The processor status register is six bits wide, and contains the current status
of five flags: Carry (F{0}), Zero (F{1}), Negative (F{2}), Overflow (F{3}), and
Interrupt (F{5}). F{4} of the register is currently reserved for future use and
its value is ignored. Each flag is affected by a variety of operations as noted
in their individual subsections. Operations whose primary target is the index
register-pair do not affect the status register.

Stack operations save and restore the entire F register as part of every
hardware stack frame; the frame format is always [PCL|PCH|F] (upper twelve bits
hold the saved program counter, lower six bits hold the status register).
Consequently, the current value of each flag is automatically preserved across
every JPS, BRK, and hardware interrupt entry and is restored by RET.


    **Interrupt Mask Flag
        The Interrupt mask flag (F{I} or 'I') serves as the master enable/disable
        control for the maskable hardware interrupt request /IRQ. When F{I} = 1, the
        processor ignores /IRQ. When F{I} = 0, an asserted /IRQ will trigger an
        interrupt entry sequence. The non-maskable interrupt /NMI, the software
        interrupt instruction BRK, and reset are never masked; they always take effect
        regardless of the state of the I flag.
       
        The I flag is only modified by the following events; it is never affected by ALU
        operations, loads, stores, transfers, or any other instruction.

        /RST signal
            On reset, the I flag is cleared along with the rest of the status
            register. See ⟪Reset/Power-on⟫ for details.
        /IRQ signal
            When /IRQ is recognized and I = 0, the program counter and status register
            are pushed onto the stack layer (S[PCL|PCH|F]) and the I flag is set
            (F{I} ← 1). The program counter is then forced to the fixed vector at
            @1774 (PC ← [@1775|@1774]). If halted, an /IRQ signal will wake the
            processor, even if masked; see ⟪Interrupt Handling⟫ for details.
        /NMI signal
            When /NMI is recognized, the program counter and status register are
            pushed onto the stack layer (S[PCL|PCH|F]) and the I flag is set
            (F{I} ← 1). The program counter is then forced to the fixed vector at
            @1776 (PC ← [@1777|@1776]). See ⟪Interrupt Handling⟫ for details.
        BRK instruction
            When BRK is executed, the program counter and status register are pushed
            onto the stack layer (S[PCL|PCH|F]) then the I flag is set (F{I} ← 1).
            BRK then forces PC to the fixed vector at @1772 (PC ← [@1773|@1772]). The
            prior value of the flag is therefore preserved in the stack frame for
            later restoration by RET. See ⟪Interrupt Handling⟫ and ⟪Detailed
            Descriptions⟫ for details.
        SEI instruction
            When SEI is executed, it explicitly sets the I flag (F{I} ← 1); no other
            flags are modified.
        CLI instruction
            When CLI is executed, it explicitly clears the I flag (F{I} ← 0); no other
            flags are modified.
        RET instruction
            When RET is executed, it pulls the top frame from the hardware stack,
            restoring both the program counter and processor status register; the I
            flag inherits the restored value.

    **Reserved F{4
        F{4} is reserved for future use. Software should neither assume a defined value
        when reading it nor rely on any effect from writing it. Like the rest of F, it
        is cleared on reset and is saved and restored as part of the stack frame.

    **Overflow Flag
        The Overflow flag (F{V} or 'V') signals whether the result of a signed 6-bit
        two's-complement arithmetic operation overflowed the representable range
        (−32..+31). The V flag is generated by arithmetic operations (with one explicit
        exception, LSL) and computed as the exclusive-OR of the carry into bit 5 and the
        carry out of bit 5:    F{V} ← (Cin{5}) ⊕ (Cout{5})
       
        The V flag is only modified by the following events; it is never affected by
        two-operand logic operations, loads, stores, transfers, index operations, or
        control-flow instructions that do not perform arithmetic.
   
        ADC, SBC, CMP, INC/DEC A instructions
            When these instructions are executed, the V flag is set (F{V} ← 1) when
            the signed result cannot be represented in six bits. The same computation
            applies whether the second operand is supplied by an immediate value, an
            absolute memory location, or an indirect memory location.
        LSL instruction
            When LSL is executed, the V flag is set to the XOR of the original bits 5
            and 4 of the accumulator (F{V} ← A{5} ⊕ A{4}); this gives a simple
            signed-overflow indication for a single-bit left shift.

    **Negative Flag
        The Negative (sign) flag (F{N} or 'N') signals the sign of the accumulator value
        by directly reflecting bit 5 of the result produced by most arithmetic, logical,
        load, shift, and compare operations:    F{N} ← result{5}
       
        The N flag is updated in parallel with the Z flag for the same group of
        operations.
       
        The N flag is only modified by the following events; it is never affected by
        stores, index operations, or control-flow instructions that do not perform
        arithmetic.
       
        Accumulator operations
            When an ALU operation targeting the accumulator is executed, the N flag is
            set or cleared (F{N} ← result{5}) based upon the result of the operation
            performed.
        LD A instructions
            When a value is loaded into the accumulator, the N flag is set or cleared
            (F{N} ← val{5}) based upon the value being loaded.

    **Zero Flag
        The Zero (equal) flag (F{Z} or 'Z') signals that the value within the
        accumulator is zero and is set (F{Z} ← 1) when the result of an operation is all
        zeros; otherwise it is cleared (F{Z} ← 0). The Z flag is updated in parallel
        with the Negative flag (N) for the majority of arithmetic, logical, load, shift,
        and compare operations.
       
        The Z flag is only modified by the following events; it is never affected by
        stores, index operations, or control-flow instructions that do not perform
        arithmetic.
       
        Accumulator operations
            When an ALU operation targeting the accumulator is executed, the Z flag is
            set or cleared (【result = 0】? ⸨F{Z} ← 1⸩ : ⸨F{Z} ← 0⸩) based upon the
            result.
        LD A instructions
            When a value is loaded into the accumulator, the Z flag is set or cleared
            (【val = 0】? ⸨F{Z} ← 1⸩ : ⸨F{Z} ← 0⸩) based upon the value being loaded.

    **Carry Flag
        The Carry flag (F{C} or 'C') indicates unsigned overflow in addition, the
        absence of a borrow in subtraction and comparison, and the bit shifted out of
        the accumulator by a shift. It is used to chain multi-word arithmetic via ADC
        and SBC.
       
        The C flag is only modified by the following events; it is never affected by
        two-operand logic operations, loads, stores, index operations, or control-flow
        instructions.
       
        ADC, SBC, CMP instructions
            After these instructions are executed, the C flag is set (F{C} ← 1) on
            carry-out from bit 5 for addition, and when no borrow is generated for
            subtraction and compare.
        INC/DEC A instructions
            After these instructions are executed, the C flag reports the carry or
            borrow from bit 5 as it does for addition and subtraction: INC A sets the
            C flag (F{C} ← 1) only on overflow from @63 → @00 and clears it otherwise,
            while DEC A clears the C flag (F{C} ← 0) only on underflow from @00 → @63
            and sets it otherwise.
        LSL, LSR instructions
            When these instructions are executed, the C flag takes on the value of the
            bit being shifted off (LSL: F{C} ← A{5}; LSR: F{C} ← A{0}).
        NOT instruction
            When NOT is executed, the C flag is forced to 1 (F{C} ← 1).
        CLC instruction
            When CLC is executed, it explicitly clears the C flag (F{C} ← 0); no other
            flags are modified.


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Reset/Power-On
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Following a reset, the program counter holds @0000 and the accumulator, index
register-pair, stack counter, and status register all hold zero. The processor
treats every reset identically, whether it occurs at initial application of
power or at any later point during operation; no distinction is made between the
two. Execution resumes by fetching the instruction at @0000. To prevent
undefined operation, refer to ⟪Memory Organization⟫ for the proper memory system
design.

Reset takes precedence over everything else the processor may be doing. An
instruction in progress does not complete, an interrupt awaiting service is
discarded, and a halt ends. No instruction defers or prevents a reset.


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Hardware Stack
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The Zg/α600 provides a dedicated hardware stack entirely separate from the
addressable memory space, consisting of eight internal storage layers. It shares
no addressing with main memory and occupies no portion of the address space.

Each layer holds a single 18-bit frame, composed of the saved program counter
and the saved processor status register in the form [PCL|PCH|F]. A push and a
pull always move a complete frame as a single unit; there is no provision for
saving or restoring PC and F independently of one another. The layer written or
read is the one identified by the stack counter; see ⟪Stack Counter⟫.

Subroutine calls and interrupt entries draw from the same eight layers rather
than from partitioned sets, so the depth available at any moment is divided
between the calls currently active and the interrupts currently being serviced.
Neither exhaustion nor underflow is detected: a ninth consecutive push overwrites
the oldest frame still held, and a pull without a corresponding push recovers
whatever that layer last contained.

On interrupt entry, PC and F are pushed as they stood immediately beforehand,
and only then is F{I} forced to 1. The saved F therefore reflects the masking
state in effect before the interrupt rather than the state the handler runs
under, and RET restores the former on return.

Reset clears the stack counter but leaves the layers themselves untouched,
holding whatever frames were present beforehand. Those frames are overwritten by
subsequent pushes rather than read back, unless a program pulls before it has
pushed, in which case it recovers a frame left over from before the reset.


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Memory Organization
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The Zg/α600 uses the von Neumann memory model: program code, data, and
peripherals all share a single, flat address space, with no architectural
distinction between instruction fetches and data accesses beyond the operation
being performed. The address space is twelve bits wide and organized into 6-bit
words, giving 4096 (4 KiW) addressable locations. Each address names exactly one
word; there is no finer granularity. The Zg/α600 defines no dedicated I/O
space—peripherals, where present, occupy ordinary addresses at the system
designer's discretion.

By convention, the lowest 1 KiW of the address space (@0000–@1777) is expected
to be ROM-resident, containing boot code and anything the processor may need to
reference before software has had the opportunity to run. The remaining 3 KiW
(@2000–@7777) is left entirely to the system designer's discretion: RAM,
additional ROM, peripherals, or any combination thereof.

This convention closes a specific hazard. Four addresses are referenced before
any software has executed—the reset target at @0000 and the three interrupt
vectors spanning @1772 through @1777—and each must hold a defined value from the
moment power stabilizes. RAM contents are not guaranteed valid at cold power-on;
only ROM, fixed at manufacture, offers that guarantee unconditionally. Because
the reset target and the vectors alike fall within the ROM-resident region, they
are valid from the first instruction a program executes, requiring no software
initialization.

The convention is a recommendation, not a processor-enforced guarantee. The
Zg/α600 has no means of knowing what physical memory is mapped to any given
address and behaves identically regardless of what the system designer places
there. A system that instead populates the low 1 KiW with RAM forgoes the
guarantee and must ensure by external means that no interrupt source—an /NMI in
particular—can reach the processor before boot firmware has established a valid
state.


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INSTRUCTION SET
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Addressing Modes
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The Zg/α600 provides four modes of addressing the system: implied, immediate,
direct, and register-indirect. Implied addressing uses single-word instructions
in which both the source and destination are defined implicitly by the opcode
itself; immediate addressing supplies a 6- or 12-bit constant or signed
displacement in subsequent instruction words (depending upon class); direct
addressing supplies a complete 12-bit memory address across two additional
words; and register-indirect mode obtains the effective address from the index
register-pair.


    **Implied Addressing
        Implied addressing mode is used when an instruction requires no address,
        immediate value, or register specifier in the instruction stream; the 6-bit
        opcode itself identifies the source and destination locations—no additional
        words are fetched. This mode covers simple register transfers, accumulator and
        index updates, basic logical operations on A, flag control, and processor-state
        instructions such as halt and software interrupt. The program counter is
        incremented by one after the instruction is read.


    **Immediate Addressing
        Immediate addressing mode is used when an instruction requires a constant
        operand or relative branch displacement that follows the opcode in the
        instruction stream; after the 6-bit opcode word is read, the class of the
        instruction determines the number of additional 6-bit words to be fetched. This
        mode covers arithmetic, logical, and comparison operations that use a constant;
        the loading of registers A, X, and Y (including the XY pair) with immediate
        values; and conditional branches that use a 6-bit signed relative offset.
        Depending on the class of the instruction, the program counter is incremented by
        either two or three after the complete instruction is read.


    **Direct Addressing
        Direct addressing mode is used when an instruction requires a full 12-bit memory
        address that follows the opcode in the instruction stream; after the 6-bit
        opcode word is read, the two additional 6-bit words containing the high and low
        halves of the absolute address are fetched ([PC+2|PC+1]). This mode covers
        jumps, subroutine calls, loads and stores, and arithmetic, logical, and
        comparison operations that access memory using a complete 12-bit address. PC is
        incremented by three after the complete instruction is read.

    **Register-Indirect Addressing
        Register-Indirect addressing mode is used when an instruction requires a memory
        address that is supplied by the index register-pair. As with implied mode, the
        6-bit opcode identifies the operation, and no additional words are fetched. This
        mode covers loads, stores, arithmetic, logical, and comparison operations, as
        well as jumps and subroutine calls, that use the current value of XY as the
        effective address. The program counter is incremented by one after the
        instruction is read.


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Encoding
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Every Zg/α600 instruction consists of one, two, or three words and begins with a
6-bit operation code (opcode) that defines the instruction and if it requires
any additional data. Utilizing variable-length instructions in this manner
trades increased decoding complexity for code density when compared to that of
fixed-length encoding.

Instructions are grouped into four classes identified by the two most
significant bits {5:4} of their opcode. Every opcode within a class shares its
one-, two-, or three-word instruction length. Each class is typically associated
with one of the four addressing modes described previously, e.g., Implied at one
word, Immediate at two, Direct at three, but class membership is defined by
length, not by strict adherence to any mode's operand-forming behavior. The sole
exception is the Register-Indirect mode, which claims a class for itself to
expedite address formation from the index registers.

The remaining four bits of each opcode {3:0} select the specific instruction
within its class; with four classes of sixteen opcodes each, the full 6-bit
opcode space is exactly and evenly divided (4 × 16 = 64 = 2^6) with no reserved
or wasted encoding space at the class level, though some individual opcodes
remain reserved within classes.


    **Class 0 // [%00]
        Class 0 comprises opcodes with {5:4} = %00. Every instruction in this class is a
        single word: the opcode itself, with no further words fetched.
       
        Membership in this class is defined by self-sufficiency: every operation it
        contains requires no additional data beyond the opcode itself to complete. This
        includes register transfers, software interrupt control, and simple accumulator
        and logical operations.

    **Class 1 // [%01]
        Class 1 comprises opcodes with {5:4} = %01. Every instruction in this class is
        two words: the opcode, followed by a second word at [PC+1].
       
        Membership in this class is defined by needing exactly one additional word of
        data to complete, regardless of how that word is used. This currently includes
        operations that take a small constant operand or conditional branches that use a
        signed relative offset.

    **Class 2 // [%10]
        Class 2 comprises opcodes with {5:4} = %10. Every instruction in this class is
        three words: the opcode, followed by a second word at [PC+1] and a third at
        [PC+2].
       
        Membership in this class is defined by needing exactly two additional words of
        data to complete, regardless of how those words are used. This currently
        includes operations that take a large constant operand or a complete 12-bit
        absolute address.

    **Class 3 // [%11]
        Class 3 comprises opcodes with {5:4} = %11. Every instruction in this class is a
        single word: the opcode itself, with no further words fetched.
       
        Membership in this class is defined by behavior rather than length: every
        operation it contains forms its effective address from the index register-pair,
        using register-indirect addressing exclusively.


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Instruction List
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Class 0                 Class 1                 Class 2                 Class 3

NOP                     LD A,#imm               LD A,abs                LD A,IXY
HLT                     LD X,#imm               ST A,abs                ST A,IXY
BRK                     LD Y,#imm               LD X,abs                LD X,IXY
RET                     ADC #imm                ST X,abs                ST X,IXY
SEI                     SBC #imm                LD Y,abs                LD Y,IXY
CLI                     CMP #imm                ST Y,abs                ST Y,IXY
CLC                     AND #imm                LD XY,#imm              ADC IXY
INC A                   OR  #imm                ADC abs                 SBC IXY
DEC A                   XOR #imm                SBC abs                 CMP IXY
INC XY                  BR ZS,rel               CMP abs                 AND IXY
DEC XY                  BR ZC,rel               AND abs                 OR  IXY
LSL                     BR CS,rel               OR  abs                 XOR IXY
LSR                     BR CC,rel               XOR abs                 JP  IXY
TAX                     BR NS,rel               JP  abs                 JPS IXY
TAY                     BR NC,rel               JPS abs
NOT                                             JPV abs


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Detailed Descriptions
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CLASS 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

NOP || No Operation
    Operation:          None
    Mode:               Implied
    Length:             1 word
    Flags affected:     None

HLT || Halt
    Operation:          suspends execution until interrupt or reset is
                        recognized
    Mode:               Implied
    Length:             1 word
    Flags affected:     None
    Notes:              An /IRQ asserted while F{I} = 1 ends the halt without
                        triggering an entry sequence; execution continues at PC
                        with no frame pushed and no vector taken.

BRK || Software Break
    Operation:          S[PCL|PCH|F] ← PC|F;
                        SC ← SC+1; F{I} ← 1;
                        PC ← [@1773|@1772]
    Mode:               Implied
    Length:             1 word
    Flags affected:     I flag set unconditionally

RET || Return
    Operation:          SC ← SC−1;
                        PC|F ← S[PCL|PCH|F]
    Mode:               Implied
    Length:             1 word
    Flags affected:     None generated; the whole of F is replaced by the
                        restored frame.
    Notes:              RET serves as the sole return path for JPS, BRK, and
                        both hardware interrupt sources alike.

SEI || Set Interrupt Mask
    Operation:          F{I} ← 1
    Mode:               Implied
    Length:             1 word
    Flags affected:     I flag set unconditionally

CLI || Clear Interrupt Mask
    Operation:          F{I} ← 0
    Mode:               Implied
    Length:             1 word
    Flags affected:     I flag cleared unconditionally

CLC || Clear Carry
    Operation:          F{C} ← 0
    Mode:               Implied
    Length:             1 word
    Flags affected:     C flag cleared unconditionally

INC A || Increment Accumulator
    Operation:          A ← A+1
    Mode:               Implied
    Length:             1 word
    Flags affected:     F{C} ← carry-out of bit 5;
                        F{V} ← Cin{5} ⊕ Cout{5};
                        F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}

DEC A || Decrement Accumulator
    Operation:          A ← A−1
    Mode:               Implied
    Length:             1 word
    Flags affected:     F{C} ← 1 if no borrow generated, else 0;
                        F{V} ← Cin{5} ⊕ Cout{5};
                        F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}

INC XY || Increment Index Register-Pair
    Operation:          XY ← XY+1
    Mode:               Implied
    Length:             1 word
    Flags affected:     None

DEC XY || Decrement Index Register-Pair
    Operation:          XY ← XY−1
    Mode:               Implied
    Length:             1 word
    Flags affected:     None

LSL || Logical Shift Left
    Operation:          A ← A≪1
    Mode:               Implied
    Length:             1 word
    Flags affected:     F{C} ← A{5};
                        F{V} ← A{5} ⊕ A{4};
                        F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}
    Notes:              C and V flags generated from pre-shift A.

LSR || Logical Shift Right
    Operation:          A ← A≫1
    Mode:               Implied
    Length:             1 word
    Flags affected:     F{C} ← A{0};
                        F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}
    Notes:              C flag generated from pre-shift A.

TAX || Transfer Accumulator to X
    Operation:          A → X
    Mode:               Implied
    Length:             1 word
    Flags affected:     None

TAY || Transfer Accumulator to Y
    Operation:          A → Y
    Mode:               Implied
    Length:             1 word
    Flags affected:     None

NOT || Bitwise Complement
    Operation:          A ← ¬A
    Mode:               Implied
    Length:             1 word
    Flags affected:     F{C} ← 1;
                        F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}
    Notes:              The forced carry provides the machine's only means of
                        seeding F{C} ← 1; the pair `NOT; NOT` leaves A unchanged
                        and sets carry ahead of a chained SBC sequence, serving
                        in place of a dedicated set-carry instruction.

CLASS 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

LD A,#imm || Load Accumulator with Immediate
    Operation:          A ← imm
    Mode:               Immediate
    Length:             2 words
    Flags affected:     F{Z} ← 1 if imm = 0, else 0;
                        F{N} ← imm{5}

LD X,#imm || Load X with Immediate
    Operation:          X ← imm
    Mode:               Immediate
    Length:             2 words
    Flags affected:     None

LD Y,#imm || Load Y with Immediate
    Operation:          Y ← imm
    Mode:               Immediate
    Length:             2 words
    Flags affected:     None

ADC #imm || Add Immediate to Accumulator with Carry
    Operation:          A ← A + imm + F{C}
    Mode:               Immediate
    Length:             2 words
    Flags affected:     F{C} ← carry-out of bit 5;
                        F{V} ← Cin{5} ⊕ Cout{5};
                        F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}

SBC #imm || Subtract Immediate from Accumulator with Carry
    Operation:          A ← A − imm − ¬F{C}
    Mode:               Immediate
    Length:             2 words
    Flags affected:     F{C} ← 1 if no borrow generated, else 0;
                        F{V} ← Cin{5} ⊕ Cout{5};
                        F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}

CMP #imm || Compare Accumulator with Immediate
    Operation:          A − imm
    Mode:               Immediate
    Length:             2 words
    Flags affected:     F{C} ← 1 if no borrow generated, else 0;
                        F{V} ← Cin{5} ⊕ Cout{5};
                        F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}
    Notes:              Accumulator remains unchanged by result.

AND #imm || Bitwise AND Immediate with Accumulator
    Operation:          A ← A & imm
    Mode:               Immediate
    Length:             2 words
    Flags affected:     F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}

OR #imm || Bitwise OR Immediate with Accumulator
    Operation:          A ← A ∥ imm
    Mode:               Immediate
    Length:             2 words
    Flags affected:     F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}

XOR #imm || Bitwise Exclusive-OR Immediate with Accumulator
    Operation:          A ← A ⊕ imm
    Mode:               Immediate
    Length:             2 words
    Flags affected:     F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}

BR ZS,rel || Branch if Zero Set
    Operation:          【F{Z} = 1】? PC ← PC+disp : —
    Mode:               Immediate
    Length:             2 words
    Flags affected:     None; branch operations only test flag state, never
                        modify it.

BR ZC,rel || Branch if Zero Clear
    Operation:          【F{Z} = 0】? PC ← PC+disp : —
    Mode:               Immediate
    Length:             2 words
    Flags affected:     None; branch operations only test flag state, never
                        modify it.

BR CS,rel || Branch if Carry Set
    Operation:          【F{C} = 1】? PC ← PC+disp : —
    Mode:               Immediate
    Length:             2 words
    Flags affected:     None; branch operations only test flag state, never
                        modify it.

BR CC,rel || Branch if Carry Clear
    Operation:          【F{C} = 0】? PC ← PC+disp : —
    Mode:               Immediate
    Length:             2 words
    Flags affected:     None; branch operations only test flag state, never
                        modify it.

BR NS,rel || Branch if Negative Set
    Operation:          【F{N} = 1】? PC ← PC+disp : —
    Mode:               Immediate
    Length:             2 words
    Flags affected:     None; branch operations only test flag state, never
                        modify it.

BR NC,rel || Branch if Negative Clear
    Operation:          【F{N} = 0】? PC ← PC+disp : —
    Mode:               Immediate
    Length:             2 words
    Flags affected:     None; branch operations only test flag state, never
                        modify it.

CLASS 2
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

LD A,abs || Load Accumulator from Absolute
    Operation:          A ← M[abs]
    Mode:               Direct
    Length:             3 words
    Flags affected:     F{Z} ← 1 if M[abs] = 0, else 0;
                        F{N} ← M[abs]{5}

ST A,abs || Store Accumulator into Absolute
    Operation:          M[abs] ← A
    Mode:               Direct
    Length:             3 words
    Flags affected:     None

LD X,abs || Load X from Absolute
    Operation:          X ← M[abs]
    Mode:               Direct
    Length:             3 words
    Flags affected:     None

ST X,abs || Store X to Absolute
    Operation:          M[abs] ← X
    Mode:               Direct
    Length:             3 words
    Flags affected:     None

LD Y,abs || Load Y from Absolute
    Operation:          Y ← M[abs]
    Mode:               Direct
    Length:             3 words
    Flags affected:     None

ST Y,abs || Store Y to Absolute
    Operation:          M[abs] ← Y
    Mode:               Direct
    Length:             3 words
    Flags affected:     None

LD XY,#imm || Load Index Register-Pair with Immediate
    Operation:          XY ← imm
    Mode:               Immediate
    Length:             3 words
    Flags affected:     None

ADC abs || Add Absolute to Accumulator with Carry
    Operation:          A ← A + M[abs] + F{C}
    Mode:               Direct
    Length:             3 words
    Flags affected:     F{C} ← carry-out of bit 5;
                        F{V} ← Cin{5} ⊕ Cout{5};
                        F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}

SBC abs || Subtract Absolute from Accumulator with Carry
    Operation:          A ← A − M[abs] − ¬F{C}
    Mode:               Direct
    Length:             3 words
    Flags affected:     F{C} ← 1 if no borrow generated, else 0;
                        F{V} ← Cin{5} ⊕ Cout{5};
                        F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}

CMP abs || Compare Accumulator with Absolute
    Operation:          A − M[abs]
    Mode:               Direct
    Length:             3 words
    Flags affected:     F{C} ← 1 if no borrow generated, else 0;
                        F{V} ← Cin{5} ⊕ Cout{5};
                        F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}
    Notes:              Accumulator remains unchanged by result.

AND abs || Bitwise AND Accumulator with Absolute
    Operation:          A ← A & M[abs]
    Mode:               Direct
    Length:             3 words
    Flags affected:     F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}

OR abs || Bitwise OR Accumulator with Absolute
    Operation:          A ← A ∥ M[abs]
    Mode:               Direct
    Length:             3 words
    Flags affected:     F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}

XOR abs || Bitwise Exclusive-OR Accumulator with Absolute
    Operation:          A ← A ⊕ M[abs]
    Mode:               Direct
    Length:             3 words
    Flags affected:     F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}

JP abs || Unconditional Jump to Absolute Address
    Operation:          PC ← abs
    Mode:               Direct
    Length:             3 words
    Flags affected:     None

JPS abs || Subroutine Jump to Absolute Address
    Operation:          S[PCL|PCH|F] ← PC|F;
                        SC ← SC+1; PC ← abs
    Mode:               Direct
    Length:             3 words
    Flags affected:     None; JPS itself does not modify any flags.

JPV abs || Jump to Absolute Address if Overflow Set
    Operation:          【F{V} = 1】? PC ← abs : —
    Mode:               Direct
    Length:             3 words
    Flags affected:     None

CLASS 3
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

LD A,IXY || Load Accumulator via Register-Indirect
    Operation:          A ← M[XY]
    Mode:               Register-Indirect
    Length:             1 word
    Flags affected:     F{Z} ← 1 if M[XY] = 0, else 0;
                        F{N} ← M[XY]{5}

ST A,IXY || Store Accumulator via Register-Indirect
    Operation:          M[XY] ← A
    Mode:               Register-Indirect
    Length:             1 word
    Flags affected:     None

LD X,IXY || Load X via Register-Indirect
    Operation:          X ← M[XY]
    Mode:               Register-Indirect
    Length:             1 word
    Flags affected:     None

ST X,IXY || Store X via Register-Indirect
    Operation:          M[XY] ← X
    Mode:               Register-Indirect
    Length:             1 word
    Flags affected:     None

LD Y,IXY || Load Y via Register-Indirect
    Operation:          Y ← M[XY]
    Mode:               Register-Indirect
    Length:             1 word
    Flags affected:     None

ST Y,IXY || Store Y via Register-Indirect
    Operation:          M[XY] ← Y
    Mode:               Register-Indirect
    Length:             1 word
    Flags affected:     None

ADC IXY || Add Register-Indirect to Accumulator with Carry
    Operation:          A ← A + M[XY] + F{C}
    Mode:               Register-Indirect
    Length:             1 word
    Flags affected:     F{C} ← carry-out of bit 5;
                        F{V} ← Cin{5} ⊕ Cout{5};
                        F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}

SBC IXY || Subtract Register-Indirect from Accumulator with Carry
    Operation:          A ← A − M[XY] − ¬F{C}
    Mode:               Register-Indirect
    Length:             1 word
    Flags affected:     F{C} ← 1 if no borrow generated, else 0;
                        F{V} ← Cin{5} ⊕ Cout{5};
                        F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}

CMP IXY || Compare Accumulator with Register-Indirect
    Operation:          A − M[XY]
    Mode:               Register-Indirect
    Length:             1 word
    Flags affected:     F{C} ← 1 if no borrow generated, else 0;
                        F{V} ← Cin{5} ⊕ Cout{5};
                        F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}
    Notes:              Accumulator remains unchanged by result.

AND IXY || Bitwise AND Accumulator with Register-Indirect
    Operation:          A ← A & M[XY]
    Mode:               Register-Indirect
    Length:             1 word
    Flags affected:     F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}

OR IXY || Bitwise OR Accumulator with Register-Indirect
    Operation:          A ← A ∥ M[XY]
    Mode:               Register-Indirect
    Length:             1 word
    Flags affected:     F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}

XOR IXY || Bitwise Exclusive-OR Accumulator with Register-Indirect
    Operation:          A ← A ⊕ M[XY]
    Mode:               Register-Indirect
    Length:             1 word
    Flags affected:     F{Z} ← 1 if result = 0, else 0;
                        F{N} ← result{5}

JP IXY || Jump to Register-Indirect
    Operation:          PC ← XY
    Mode:               Register-Indirect
    Length:             1 word
    Flags affected:     None

JPS IXY || Jump to Subroutine via Register-Indirect
    Operation:          S[PCL|PCH|F] ← PC|F;
                        SC ← SC+1; PC ← XY
    Mode:               Register-Indirect
    Length:             1 word
    Flags affected:     None; JPS itself does not modify any flags.


--------------------------------------------------------------------------------
Opcode Map
--------------------------------------------------------------------------------

columns select class ({5:4}), rows select opcode-within-class ({3:0})


        Class 0      Class 1      Class 2        Class 3
          %00          %01          %10            %11

%0000   NOP          LD A,#i      LD A,ab        LD A,IX
%0001   HLT          LD X,#i      ST A,ab        ST A,IX
%0010   BRK          LD Y,#i      LD X,ab        LD X,IX
%0011   RET          ADC #i       ST X,ab        ST X,IX
%0100   SEI          SBC #i       LD Y,ab        LD Y,IX
%0101   CLI          CMP #i       ST Y,ab        ST Y,IX
%0110   CLC          AND #i       LD XY,#i       ADC IX
%0111   INC A        OR  #i       ADC ab         SBC IX
%1000   DEC A        XOR #i       SBC ab         CMP IX
%1001   INC XY       BR ZS,rel    CMP ab         AND IX
%1010   DEC XY       BR ZC,rel    AND ab         OR  IX
%1011   LSL          BR CS,rel    OR  ab         XOR IX
%1100   LSR          BR CC,rel    XOR ab         JP  IX
%1101   TAX          BR NS,rel    JP  ab         JPS IX
%1110   TAY          BR NC,rel    JPS ab         R
%1111   NOT          R            JPV ab         R