Elsewhere I was reminded that Ivan Godard of Out-of-the-Box Computing is currently releasing presentations about his new CPU architecture (presently simulated, not yet fabricated.)
[Edit:] It's sort of VLIW, with up to 33 operations per cycle. "If the Mill can pull this off, you'll get a CPU that can get a 10x better performance-per-power rating, and that on a smaller die" - commenter on Reddit.
There are various ideas here - dual PCs travelling in opposite directions, for example - but perhaps the most visible feature is that there's no register file, nor a register stack, but a moving queue of registers of some specific length. Results are plucked out of the queue before they fall off the end, the timing and location of the results depending on the fact that all instruction latencies are fixed (for a given implementation.)
"in the coming months, we will add sections for the Belt, Operands and Data, the Memory Hierarchy, Protection, Software Pipelining, Branch Prediction, and other areas."
See
http://staff.science.uva.nl/~poss/posts ... /mill-cpu/http://www.reddit.com/r/programming/com ... _metadata/and various videos and presentations:
http://www.youtube.com/watch?v=jNgIdTUmzEQhttp://ootbcomp.com/docs/