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 [ 10 posts ] 
 OT: economics of chip production 
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1772
These days we can put our designs on relatively high performance and high capacity FPGAs.

But from time to time the idea pops up that it would be great to make a custom chip. As it turns out, the economics of doing that are rather forbidding - although there is a special case of doing an FPGA design and getting it "hardened" into a chip for that single purpose ,and the even simpler idea of putting a design into a non-volatile FPGA, or just selling an EEPROM with the appropriate bitstream already stored in it. Here's a comment on HN which gives a price point:

I'm the founder of a startup taping out of first test chip in May... Getting 100 chips back on a shuttle run (Also known as a multi project wafer, where mask costs are shared by multiple companies) will cost us around $250,000. That is just the cost of these first 100 chips. Mask costs for a modern (eg 28nm) process start at about $2 Million, and go up from there pretty quickly, but is based on a lot of factors. Once the masks are made though, it is roughly $5K a wafer (where you can have 100s of dies on a wafer.)

The rest of the thread might be worth a look too.

Fri Jan 08, 2016 11:32 am

Joined: Wed Jan 16, 2013 2:33 am
Posts: 165
I have actually heard $6,000 for a run of integrated circuits. ... make-an-ic

Let me know what you think and please see Ken's response.

I think they used Laker (spelling) as CAD software in the past to design their chips. The license back then was $40,000 or 27552.86 British Pounds (conversion according to Google). You could probably buy a luxury car for that amount of money. When you design something that small, you probably need some experience or check for electrical leaks because I've heard chips leak electricity.

Fri Jan 08, 2016 7:04 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1772
Yes, the usual suite of design tools would set you back millions for a reasonable design team. Your fabless silicon startup probably needs $100 million of funding. But of course, you can also use cheap tools - maybe even free tools. Or you can pay an external design house to do the work using their licensed tools.

The cost of masks, wafers and processing is, as said, a function of process technology. Design behind the curve and your chip will be bigger but possibly cheaper. Your source says
Depending on the process, design size and overall volume wafers can be from $600 to $2000 each.

and I really don't know in what circumstances that holds. The minimum quantity would (I believe) normally be a half lot, which is (it seems) 12 wafers.

I'm afraid I have no useful numbers in my head, so the best I can do is quote from hopefully credible sources.

If you were thinking of building a fab (and you weren't), it looks like that would be $2-3 billion and process 30,000 wafers per month. Although that's 20 years ago...

Fri Jan 08, 2016 7:45 pm

Joined: Wed Jan 16, 2013 2:33 am
Posts: 165
BigEd wrote:
If you were thinking of building a fab (and you weren't), it looks like that would be $2-3 billion and process 30,000 wafers per month. Although that's 20 years ago...

I believe they contract out and use foundries that are willing to produce a chip.
They do a lot of testing so I don't know what the quality is but I am sure it is factored in so they can make a profit.

Fri Jan 08, 2016 8:15 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1772
Indeed, there are really not many outfits that run state of the art fabs. Used to be many more. But there are enough for a little competition.

Again, a design on a trailing edge process can go to a lesser player for a lower price.

If you search you can probably find breakdowns of design cost, mask cost, wafer cost, testing and packaging costs. If you're thinking about commercial operations then there will also be the distributor's markup.

For a retro project, the difficulty is that you need to shift probably thousands or tens of thousands of chips, and you need six or seven digits of funding to make those chips in the first place.

Oh, look, here's a blog post by a chip maker laying out some of this: ... omics-101/

Fri Jan 08, 2016 8:25 pm

Joined: Wed Jan 16, 2013 2:33 am
Posts: 165
Very good information.

It might be why some of the larger companies have a harder time listening to customers. There is too much money involved.

Fri Jan 08, 2016 8:38 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1772
Absolutely - even the most avid hobbyist isn't going to buy ten thousand chips. If all customers need the same amount of assistance, only the largest ones are going to get it.

There's an amusing die-per-wafer calculator at ... -per-wafer
which you can dial down to 2 inch wafers or all the way up to 12 inch. See how much difference it makes between the size of a 6800 and 6502!

6502 is 3.9 x 4.3 giving 165 die on a 3 inch wafer
6800 is 5.4 x 5.4 giving 92 die on a 3 inch wafer

Larger chips have lower yield, so even before MOS applied their yield-enhancing techniques, the 6800 is well over twice the cost to make. (Assuming both outfits pay about the same per wafer)

(If the 6800 is on a simpler process, and with fewer masks, that helps Moto.)

There's also a cost calculator at ... alculator/
but you need to decide on a yield.

Fri Jan 08, 2016 8:41 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1772
More info from Mr. adapteva:

Q. How much markup over material costs is there on most chips?

A. There is no typical...but here are some guidelines
1.2x (companies are either ultra efficient, copycats, suicidal, or dumping)
2x (US companies shipping volume, healthy)
4x (goal for FPGA companies and mixed signal niche)
10x (goal for companies with monopolies)
100x (one-offs, like processors for military/satellite)

More here.

Mon Jan 11, 2016 3:04 pm

Joined: Thu Sep 22, 2022 10:00 am
Posts: 1
With regards to chip production economics, the industry is looking into producing 450mm wafers (18" inch) which mean that the silicon fab will be able to output more dies per wafer for almost the same price. I found this die per wafer calculator to be accurate because its taking into account the edge protection of a wafer. Link: ... lculators/

Thu Sep 22, 2022 10:03 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 533
Do they still do gate array syle logic? Say if one wanted to recreate the ZX Spectrum today rather than in the 1980's.

Thu Sep 22, 2022 5:26 pm
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