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 [ 4 posts ] 
 MMU models and functionality? 
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Joined: Thu Jan 17, 2013 4:38 pm
Posts: 54
(I'll be posting several more when I remember all subtopics)

Have any CPUs split the MMU in a separate instruction and data MMU? Any immediate pros and cons for doing this?
(I was thinking at 2x the size or number of mmu entries with hopefully no extra slowdown, and possibly tuning mapping sizes to fit the characteristics of either.)


Thu Feb 14, 2013 12:48 pm

Joined: Thu Jan 17, 2013 4:38 pm
Posts: 54
Have any CPUs used MMU status bits to define per-page endianness, priviledge level (ring) or priviledge escalation permission? (or any related ideas)


Thu Feb 14, 2013 2:29 pm

Joined: Sat Feb 02, 2013 9:40 am
Posts: 2101
Location: Canada
I believe some versions of the MIPS processors use multiple TLB's to support independent data and code lookups. There's a TLB for code, a TLB for data, then a thrid joint TLB (micro TLB) that is shared for both code and data.

I wonder if there's a processor out there that has more independent MMU's for things like stack, and I/O.

I was just working on code for a 6829 MMU look-a-like teh other day.

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Robert Finch http://www.finitron.ca


Fri Feb 15, 2013 3:03 pm WWW

Joined: Wed Jul 24, 2013 10:17 pm
Posts: 3
NorthWay wrote:
(I'll be posting several more when I remember all subtopics)

Have any CPUs split the MMU in a separate instruction and data MMU? Any immediate pros and cons for doing this?
(I was thinking at 2x the size or number of mmu entries with hopefully no extra slowdown, and possibly tuning mapping sizes to fit the characteristics of either.)


Most processors which have an MMU have separate instruction and data TLBs.

Toshi


Wed Jul 24, 2013 10:35 pm
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