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 [ 4 posts ] 
 What are you working on? What ideas do you have? 
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1647
As we're not seeing much activity in the Projects area of this forum, and as people might well be leaving their record of their work elsewhere, and as we often find we have more ideas for projects than projects in progress, I thought it might be worth asking: what microprocessor or CPU projects do you have in flight, or lined up on the runway?

Photos or links to blogs or repositories would be extra nice, but any kind of semi-organised description would be fine!

(By all means start a thread in the Projects area for discussion of your project - but perhaps drop a mention here too.)


Thu Oct 13, 2016 4:56 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1647
For myself, I seem mostly to be acting as an assistant while other people make the progress. This is normal.

Ongoing:
- the emulation of 6502 and other CPUs on baremetal Raspberry Pi, as an 8-bit peripheral/coprocessor

Pending or barely started:
- the analysis of the custom chip in Acorn's Electron
- testing a banked-RAM 6502 in FPGA with an eye to Fuzix
- an 8 bit ROM board or emulation of ROM using a Pi
- the analysis of an obscure British microprocessor and its peripherals

Ideas:
- some analysis of 6502 traces to see what cache organisations might have what effect
- arduino something something
- raspberry pi something something
- FPGA something something


Thu Oct 13, 2016 4:58 pm

Joined: Wed Apr 24, 2013 9:40 pm
Posts: 206
Location: Huntsville, AL
Beyond the work on completing the M65C02A project, I am working on these projects:

    1) Cleaning up and adding to the M65C02 wiki
    2) Completing the port of the Mak 8086 Pascal Compiler to the M65C02A
    3) Working toward implementing an M65C02A assembler for Py65
    4) Continuing to work on the MiniCPU-S
    5) Converting the M65C02A and M16C5x (or on anycpu.org: M16C5x) into a Symmetrical Multi-Threaded (SMT) or Barrel processors
    6) Doing a lot of study on computer architectures, programming languages, operating systems, etc.
    7) Writing up the work that I've been doing the past few years in a blog on FPGARelated

I expect to release something on the M65C02A version of the Mak Pascal compiler soon. I'm in the process of completing the code generator modules/functions. I do this in small steps. Professor Mak has provided a number of reference programs that he used to test his compiler. I am slowly building up the code generator with these programs in order to get the fundamentals correct, and then add in some of the more advanced functions that may finally require me to complete the design and implement the co-processor module for the M65C02A.

I have added to instructions to support the operations required by the Pascal compiler:

    1) xma sp16,S
    2) adj #imm

The xma instruction exchanges memory with the accumulator. The location is a 16-bit offset from the stack pointer. It specifically addresses a problem I encountered processing arguments for a subtraction operation when the left and right operands are in the wrong order on the stack because of the left to right evaluation of expressions performed by the recursive descent Mak Pascal compiler. XMA is more general purpose, and can be used to easily implement FORTH stack operations.

The adj instruction adds a signed immediate value (which defaults to 8-bits, but can be extended to 16-bits) to the system stack pointer. The instruction provides an easy way to remove the parameters and local variables allocated on the stack by a procedure/function. Instead of supporting the Pascal stack clean up mechanism where the procedure/function cleans up the stack, I decided it would be more appropriate to support the C stack clean up mechanism: the caller cleans up the stack. The 8086 subroutine return instruction provides direct support for the stack frame clean up, but I did not want to add anymore temporary registers to the core in order to support the Pascal stack frame clean up mechanism directly.

I have three (maybe four) unused/reserved opcodes remaining in the instruction set map of the M65C02A. I may use one of these opcodes to implement a second Load Effective Address (LEA) instruction. The first lea instruction is the M65C02A PSH #imm16 instruction (otherwise known as the '816 PEA #imm16 instruction), but this instruction only supports the Load Effective Address mechanism for global, level 1 variables and constants. Within Pascal, the address of most variables is relative to the stack frame base pointer. The frequent use of the 8086 lea instruction for this case means that there is a significant amount of code (or subroutine calls) to compute the effective address of variables at different levels in the stack. Therefore, I am thinking of implementing an lea bp,B instruction with support for 8-bit or 16-bit offsets. For a memory restricted processor like the 6502/65C02, it makes some sense that the local variable space within a subroutine/function will be less than 128 16-bit memory locations. But if the microprogram memory is available, I'll try and provide a more general solution by supporting 8-bit and 16-bit offsets.

Another operation not directly supported by the 6502/65C02 is negation. Unary minus operations are not the frequent, so this would be a nice to have instruction. Finally, I've had to add php/plp instructions around the accumulator load instructions that set up the boolean values used for logical tests. I may think about adding a load instruction that does not modify the processor status word to simplify the construction of the boolean test results in the accumulator.

_________________
Michael A.


Fri Oct 14, 2016 4:42 am

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1531
Location: Canada
I’ve been working on mainly software lately (along with playing games). I suppose I could put a post under software but its a game that I'm working on so I'm not sure how relevant it is to the forum.

I’ve also been working on a new 32 bit core called Dark-Star-Dragon or DSD7 for short. The core is about 10k logic cells (6k LUTs) and fits into 1/3 of an xc7a35. About 1/3 of the core’s resources are for a 4kiB 4-way set associative instruction cache. Features compressed instruction sets. 16,32, and 64 bit instructions. I hope to fit an entire SoC into a 7a35. In the long term the core will be superscalar. It should be more efficient than the Thor core.

Software: I’ve been working on a planetary emulation (Civilization) type game. In the long run I hope to have a first-person viewpoint available. So I’ve been studying graphics. At the moment I’m dealing with out of memory problems, the game could be managing around 500,000 bitmaps possibly a lot more. (5000+ units x 8 directions x 10+ frames of animation). There is a separate bitmap for each frame of animation. Each bitmap is approximately 80x80. So at 256 colors per bitmap it takes 3.2GB of memory. Unfortunately I’m using a free compiler which I think doesn’t support 64 bit address space.

A few months ago I was working on a 6567 replacement board. Got as far as designing a level shifting interface board to an FPGA board. Some verification of the circuit was done. But I really got bogged down when it reached the point I needed a C64 to test with.

_________________
Robert Finch http://www.finitron.ca


Sat Oct 15, 2016 2:32 am WWW
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