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 Author: joanlluch [ Sat Oct 05, 2019 4:36 pm ] Post subject: Re: One Page Computing - roll your own challenge Hi Revaldino.Thanks for taking the time to write these macros. It's quite interesting and fully reflects the design constraint of the OPC designs. I can't wait to see whether the application of the 'condition flag' along with the others that you propose makes this better without adding too much hardware.With the risk of being a bit off-topic, but motivated by Ed's comment above on the Risc-V. I researched a bit, and found a RISCV implementation of 'multiply' in assembler.Code:   .globl __mulsi3   .type  __mulsi3, @function__mulsi3:   mv     a2, a0   mv     a0, zero.L1:   andi   a3, a1, 1   beqz   a3, .L2   add    a0, a0, a2.L2:   srli   a1, a1, 1   slli   a2, a2, 1   bnez   a1, .L1   retIt's quite interesting how compact it is. By looking at what it does, I'm pretty sure that the original C code (assuming this was compiler generated) was this:Code:unsigned int __mulsi3 (unsigned int a, unsigned int b){  unsigned int r = 0;  while (a)  {    if (a & 1)      r += b;    a >>= 1;    b <<= 1;  }  return r;}Just as a matter of curiosity, I took one step further and tried to compile that C code in LLVM for the RISCV-32 architecture. The result was this:Code:   .globl   __mulsi3   .type   __mulsi3,@function__mulsi3:   mv   a2, zero   beqz   a0, .LBB0_2.LBB0_1:   andi   a3, a0, 1   neg   a3, a3   and   a3, a3, a1   add   a2, a3, a2   slli   a1, a1, 1   srli   a0, a0, 1   bnez   a0, .LBB0_1.LBB0_2:   mv   a0, a2   retSo not quite the same as the original, but pretty close. The difference is that there's an early exit when 'a' is zero, and the internal branch is replaced by a series of branch-less operations that should do the same. I suppose that one or the other might be better depending on branch prediction efficiency on the target hardware. I found that the LLVM compiler tends to consider branches as next to hell, so this output is consistent with that approach. The RISC-V is definitively an architecture to look at when trying to design our own cpus...Joan

 Author: joanlluch [ Sat Oct 05, 2019 6:16 pm ] Post subject: Re: One Page Computing - roll your own challenge joanlluch wrote:Hi Revaldino.Thanks for taking the time to write these macros. It's quite interesting and fully reflects the design constraint of the OPC designs. I can't wait to see whether the application of the 'condition flag' along with the others that you propose makes this better without adding too much hardware.With the risk of being a bit off-topic, but motivated by Ed's comment above on the Risc-V. I researched a bit, and found a RISCV implementation of 'multiply' in assembler.Code:   .globl __mulsi3   .type  __mulsi3, @function__mulsi3:   mv     a2, a0   mv     a0, zero.L1:   andi   a3, a1, 1   beqz   a3, .L2   add    a0, a0, a2.L2:   srli   a1, a1, 1   slli   a2, a2, 1   bnez   a1, .L1   retIt's quite interesting how compact it is. By looking at what it does, I'm pretty sure that the original C code (assuming this was compiler generated) was this:Code:unsigned int __mulsi3 (unsigned int a, unsigned int b){  unsigned int r = 0;  while (a)  {    if (a & 1)      r += b;    a >>= 1;    b <<= 1;  }  return r;}Just as a matter of curiosity, I took one step further and tried to compile that C code in LLVM for the RISCV-32 architecture. The result was this:Code:   .globl   __mulsi3   .type   __mulsi3,@function__mulsi3:   mv   a2, zero   beqz   a0, .LBB0_2.LBB0_1:   andi   a3, a0, 1   neg   a3, a3   and   a3, a3, a1   add   a2, a3, a2   slli   a1, a1, 1   srli   a0, a0, 1   bnez   a0, .LBB0_1.LBB0_2:   mv   a0, a2   retSo not quite the same as the original, but pretty close. The difference is that there's an early exit when 'a' is zero, and the internal branch is replaced by a series of branch-less operations that should do the same. I suppose that one or the other might be better depending on branch prediction efficiency on the target hardware. I found that the LLVM compiler tends to consider branches as belonging to hell, so this output is consistent with that approach. The RISC-V is definitively an architecture to look at when trying to design our own cpus...Joan

 Author: oldben [ Thu Oct 10, 2019 7:56 pm ] Post subject: Re: One Page Computing - roll your own challenge How about this idea, not a page design but a one page description.

 Author: monsonite [ Sun Oct 20, 2019 1:32 pm ] Post subject: Re: One Page Computing - roll your own challenge I think it was the OPC Challenge that inspired me first to join anycpu.org and get involved with simpler computers back in 2017.Putting artificial constraints on a project certainly focuses the mind to keep things simple.This week I have written a cpu simulator for my Suite-16, 16-bit cpu, which runs on any Arduino compatible board in less than 60 lines of C++ code.Perhaps the TTL implementation of the Suite-16 cpu will be in fewer than 66 TTL ICs I have started a Github Repository for the project Here's the simulator running a Hello World! program on an Arduino:https://github.com/monsonite/Suite-16/b ... orld_1.inoand the project on Hackaday.io is here: https://hackaday.io/project/168025-suite-16/detailsLooking back at the original challenge, 66 lines of 132 column fan-fold paper - that's more than 8K characters of sourcecode - which should be enough for most die-hards.

 Author: BigEd [ Fri Jan 24, 2020 8:45 am ] Post subject: Re: One Page Computing - roll your own challenge Nearby, B.Bibby has found a four-instruction machine with a one page Verilog model:viewtopic.php?p=5336#p5336

 Author: robfinch [ Wed Mar 25, 2020 4:36 am ] Post subject: Re: One Page Computing - roll your own challenge I’ve got a start on a new one-page-challenge cpu. Called FT20200324 (the date) for lack of a better name. It’s a 32-bit risc, 32 register machine with instruction predicates. 16 predicate registers. 1 Link register. Basic instruction formats are as follows:Code:// {RR}:   pppp 00010 ttttt aaaaa bbbbb oooooooo// ADD:      pppp 00010 ttttt aaaaa bbbbb 00000100// SUB:      pppp 00010 ttttt aaaaa bbbbb 00000101// AND:      pppp 00010 ttttt aaaaa bbbbb 00001000// OR:      pppp 00010 ttttt aaaaa bbbbb 00001001// XOR:      pppp 00010 ttttt aaaaa bbbbb 00001010// MUL:      pppp 00010 ttttt aaaaa bbbbb 00001011// SHL:      pppp 00010 ttttt aaaaa bbbbb 00010000// SHR:      pppp 00010 ttttt aaaaa bbbbb 00010001// ASR:      pppp 00010 ttttt aaaaa bbbbb 00010010// RET:      pppp 00010 00000 ----- ----- 10000000// NOP:      pppp 00010 00000 ----- ----- 11101010// Cxx:      pppp 00010 -PPPP aaaaa bbbbb 1111oooo// ADDi:   pppp 00100 ttttt aaaaa nnnnnnnnnnnnn// ANDi:   pppp 01000 ttttt aaaaa nnnnnnnnnnnnn// ORi:      pppp 01001 ttttt aaaaa nnnnnnnnnnnnn// XORi:   pppp 01010 ttttt aaaaa nnnnnnnnnnnnn// LD:      pppp 10000 ttttt aaaaa nnnnnnnnnnnnn// ST:      pppp 10001 sssss aaaaa nnnnnnnnnnnnn// ADDIS:   pppp 1001n ttttt nnnnnnnnnnnnnnnnnn// JMP:      pppp 10111 l aaaaaaaaaaaaaaaaaaaaaa// Cxxi:   pppp 11ooo oPPPP aaaaa nnnnnnnnnnnnn// A ton of compares including a generate carry into predicate register According to the toolset it should run at 120MHz+ (without multiply) with most instructions being single cycle. The multiply operation slows things down to about 75MHz.Core size is about 2600 LC’s.

 Author: BigEd [ Wed Mar 25, 2020 6:29 am ] Post subject: Re: One Page Computing - roll your own challenge Impressive! Do please start a thread about it and give the full run-down!

 Author: B.Bibby [ Thu May 14, 2020 6:46 pm ] Post subject: Re: One Page Computing - roll your own challenge Another candidate for the OPC challenge?A FPGA based Harvard style 8 bit CPU in 66 lines of SpinalHDL.https://justanotherelectronicsblog.com/?p=543

 Author: BigEd [ Thu May 14, 2020 7:21 pm ] Post subject: Re: One Page Computing - roll your own challenge Great find! And I notice revaldinho gets a namecheck too.