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 Minimum Instruction Set Computers (MISC) 
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Joined: Mon Aug 14, 2017 8:23 am
Posts: 157
Hi All,

Back in the 1990's Chuck Moore (Forth) and Jeff Fox were working on a new class of microprocessors that were low hardware overhead and very small instruction set.

Sadly Jeff Fox died a few years ago - but a lot of his work has been preserved on his website.

Here's a little taster - describing Jeff and Chuck's Mup21 - a MISC Forth processor



Mon Oct 02, 2017 5:55 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1690
What is the minimum set of instructions in a practical microprocessor? The CISC processors generally have 100 or more instructions. The RISC processors have about 50 instructions. In our investigations, it was obvious that 16 instructions are not sufficient to support all the necessary functions required in a microprocessor. 50 instructions are too many. The minimum number of instructions is somewhere between 16 and 32. A convenient choice is to limit the number of instructions to 32 and implement a microprocessor with 5 bit instructions.

It does seem to be a bit of a sweet spot, 16 or a bit more. Even our OPC5ls ended up at 17 instructions(!) and the OPC6 went on into the 20s. What we were doing was trying to minimise the complexity of the implementation. An alternative, and perhaps this is the way to look at this MISC project, is to aim to minimise the difficulty of supporting a particular application or HLL.

I recently read something about the whole RISC vs CISC, and the line it took was this: we pretty much know what a RISC looks like, it will have 5 or 6 properties out of 6 or 7 defining properties. And CISC, really, is everything else! Say that you have a RISC, and you could make a reasonable set of guesses about what it's like, whereas a CISC can look like anything.

An OISC on the other hand (that's the 4th hand now) is mostly of theoretical, esoteric, or impractical interest.

Tue Oct 03, 2017 9:15 am

Joined: Mon Aug 14, 2017 8:23 am
Posts: 157

Thanks for those links - I found Al Williams "One-Der" transport triggered architecture most interesting. ... 122?pgno=1

This sheds some light on the Maxim Maxq - which is a similar architecture - and incorporated into a number of Dallas/Maxim ICs - such as their "Fuel Gauge" for battery systems and the curiously named "System Management Microcontroller" the MAX31782 - I think a multichannel fan-speed controller for server systems

There's some detail about it in this GoogleBook ... xq&f=false



Tue Oct 03, 2017 9:59 am

Joined: Tue Aug 08, 2017 1:33 pm
Posts: 7
A sort-of interesting take on the OISC idea is using a single instruction of recent x86 processors:

While looking for that paper, I found this:

Tue Oct 03, 2017 10:58 am

Joined: Mon Aug 14, 2017 8:23 am
Posts: 157
Whilst searching for more information on Charles Moore's muP21 I came across this thesis from about 10 years ago - which looks at stack computer architecture - taking up the story from the point where Philip Koopman's book ends. ... ecture.pdf

Fri Oct 06, 2017 7:26 am

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1690
These are all good finds - I won't have a chance to read until next week...

Fri Oct 06, 2017 8:31 am

Joined: Wed Apr 24, 2013 9:40 pm
Posts: 210
Location: Huntsville, AL
Dr. LaForest, now. has on ongoing CPU project over on github that may be of interest: Octavo. I've been following some of his work since finding the thesis linked above several years ago.

Phillip Koopman's book on stack processors is also a good read, and describes a number of Forth processor architectures. I enjoyed the PDF version of the book enough that I bought a copy from a used book dealer. For those interested in processors supporting FORTH natively, Koopman has a number of articles on the subject.

Michael A.

Fri Oct 06, 2017 11:57 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1690
Quick quote from the thesis intro:
In this thesis, I develop historical, qualitative, and quantitative distinctions between the first and second generations of stack computers. I present a rebuttal of the main arguments against stack computers and show that they are not applicable to those of the second generation. I also present an example of a small, modern stack computer and compare it to the MIPS architecture. The results show that second-generation stack computers have much better performance for deeply nested or recursive code, but are correspondingly worse for iterative code. The results also show that even though the stack computer’s zero operand instruction format only moderately increases the code density, it significantly reduces instruction memory bandwidth.

There's a good hint there that dynamic statistics might be quite different from static statistics, which is a useful warning, given the difference in effort needed to collect the two.

Tue Oct 24, 2017 8:11 am
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