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From the latest RISC-V workshop proceedings, SiFive described their upcoming SoC (which includes a 'ChipLink' to your FPGA design.) There's a small housekeeping core and four high performance cores, each with L1 cache, and a shared L2. The cores run at 1.5GHz.

See the PDF here.

What surprised me most was the amount of chip area dedicated to the DDR interface:


Quoted Performance:

• 1.7 DMIPS/MHz
• 2.75 CoreMark/MHz

Of course it doesn't have to run Linux, but that you can is an indication of the CPU capabilities.

Color me impressed. I hope this project becomes a great success. How much is this going to cost?

The video for that presentation: https://www.youtube.com/watch?v=Mp6znwaZ5xo

Also, one of my favourites from the same conference so far: The Maxion supercomputer-on-a-chip, presented by industry veteran Dave Ditzel (Sun/SPARC, Transmeta/Crusoe). 4000 RISC-V cores, designed for a 7nm process. https://www.youtube.com/watch?v=f-b4QOzMyfU

Thanks for the links. A couple of useful summaries of the two days:
http://www.lowrisc.org/blog/2017/11/sev ... p-day-one/
http://www.lowrisc.org/blog/2017/11/sev ... p-day-two/

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Making this into something of a RISC-V thread... this talk is a good one for seeing the interaction of micro architecture and physical design. Those ten port register files are not going to place and route themselves.

BOOM v2: An Open Source Out Of Order RISC V Core [video]

I'm tempted to try and learn CHISEL now. I'm wondering how it would compare to a straight vhdl or Verilog coding. It sounds like it does a lot of the work of connecting things. There seems to be a lot of LOC to BOOM though. 16,000 LOC, I think I'm sitting at < 10,000 Verilog for my own. The LOC has to be manageable for the size of the project.

I'm guessing two write, and four pairs of read ports. It looks like it wasn't using an sram template of any sort.

All the videos look like a move to popularize RiSC-V. The pundit's say RiSC-V, but I prefer my own cores.