We start by looking back at 50 years of computer architecture, where philosophical debates on instruction sets (RISC vs. CISC, VLIW vs. RISC) and parallel architectures (NUMA vs clusters) were settled with billion dollar investments on both sides. In the second half, we look forward. First, Moore's Law is ending, so the free ride is over software-oblivious increasing performance. Since we've already played the multicore card, the most-likely/only path left is domain-specific processors. The memory system is radically changing too. First, Jim Gray's decade-old prediction is finally true: "Tape is dead; flash is disk; disk is tape." New ways to connect to DRAM and new non-volatile memory technologies promise to make the memory hierarchy even deeper. Finally, and surprisingly, there is now widespread agreement on instruction set architecture, namely Reduced Instruction Set Computers. However, unlike most other fields, despite this harmony has been no open alternative to proprietary offerings from ARM and Intel. RISC-V ("RISC Five") is the proposed free and open champion. It has a small base of classic RISC instructions that run a full open-source software stack; opcodes reserved for tailoring an System-On-a-Chip (SOC) to applications; standard instruction extensions optionally included in an SoC; and it is unrestricted: there is no cost, no paperwork, and anyone can use it. The ability to prototype using ever-more-powerful FPGAs and astonishingly inexpensive custom chips combined with collaboration on open-source software and hardware offers hope of a new golden era for hardware/software systems.

The video is organized in three sections where Patterson does the first, Hennessy, does the second, and they both do the third and the questions that follow:

History of Architecture – Mainframe, Minicomputer, Microprocessor, RISC vs CISC, VLIW
Current Architecture Challenges – Ending of Dennard Scaling and Moore’s Law, Security
Future Architectural Opportunities – Domain Specific Languages and Architecture, Open Architectures, Agile Hardware Development

It’s an excellent lecture and well worth watching. Skip to the 6:10 point to get past the dead air and introduction: