Does anyone have any experience working with processors that are specialised for IO? The only one I'm really familiar with is the Intel 8089, but there must be other designs out there, and I'd like to get a feel for what other people have done in this field (as I'm currently planning designing something similar myself).

In case you're not familiar with it, the Intel 8089 is an IO Coprocessor designed to work with an 8086 or 8088 (it uses the same connection system as the 8087 maths coprocessor, so you can give it instructions embedded in the stream of instructions for the main processor) that allows you to set up two "channels" that can send and receive data between IO devices and main memory through simple programs that can transform the data and send instructions to manage the IO devices. It's basically a DMA controller on steroids.

As I see it, the limitations of the 8089 are:

• Only allows two channels, which is very limiting
• Closely tied to the 8086 architecture, so can't easily be used with other processors.
• Relies on main memory for bulk storage, so if you want a queue of data, you're going to have to (1) contend with the main processor to get it and (2) wait for what's probably fairly slow DRAM timings.

I'm thinking of a design that's:

• 8 bit rather than the 16 bits of the 8089, but:
• handles many channels (e.g. 16)
• has a small, fast SRAM for use in buffering, storing instructions, and so on, so that it can work more efficiently

Does anyone have any experience with similar systems, or thoughts about features that should be including in such a design? Instruction set design?

I'm designing this as part of a project that is designed to explore what would have been possible to achieve in 1982 or thereabouts, with only the benefit of hindsight. Therefore available components in 1982 are going to influence my design. Noticeably, the major decision of how many channels to support is being influenced by the existence of the 74AS870 (which is alas obsolete and *very* hard to find, so I'll be regretfully implementing this (at least partially) in a CPLD rather than with period-correct chips, but I'll be *designing and simulating* it with those chips before converting it over).

Sorry, no experience or thoughts, but it sounds interesting! I/O channels were the kind of feature which distinguished the more capable computers before the age of micros, and seem to have been missing since then.

The twin dual-ported 4x16 register file chip '870 is a good find too! Even if one can't get the chip, it stands as an example of a building block which must have been useful at the time.

If you're looking for inspiration regarding an I/O processor, consider the Peripheral Processors (PP) of the CDC 6600.

They are small processors (12-bit everything) used to implement the I/O for the first supercomputer. Their capabilities are limited, and they operate using time multiplexing of a single ALU. The implementation is frequently drawn as a barrel of registers around a common ALU. Hence they are known as barrel processors. You can find a good information on their operation and implementation at bitsavers.org.

This is one of my favorite processors. It's program and data requirements are such that it/they map very well into the block RAMs of Xilinx/Altera FPGAs, and maybe the Lattice and Micro Semi FPGAs. You'd probably have to write your own assembler, but the instruction set is small.

Bit of amusing background from Lawrence Liddiard's Seymour Cray's Machines (Part 2): "The CDC 160, rumored to have been designed over a weekend by Cray, was CDC's first $60,000 desk (not desktop) computer that became the prototype I/O processor for the peripheral processors surrounding the CDC 6600 and 7600." (PDF here, with Part 1 here.)

That's from a footnote in Wikipedia's CDC 160 series page, in turn linked to from the CDC 6600 page.

I've just posted some thoughts inspired by the CDC 6600 links up on my hackaday page for this project:

https://hackaday.io/project/159826-io88 ... -processor

any comments are welcome.

From your opening comments on Hackaday, it appears that you have the beginnings of a plan. Will be looking forward to the results.

Drop a note here from time to time to let us know of your progress.

I like your plan a lot, Periata. Sounds like a very ambitious one to me. Did you make any progress yet?