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 The K-Machine from Lisp Machines, Inc. 
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1690
An architectural overview of an innovative machine which was never released.

"The LMI K-machine was the last processor designed and built by Lisp Machine, Inc. Unlike other Lisp Machines, the K-machine is not descended from Tom Knight's original CONS architecture; the K-machine is an original design. This paper provides an overview of the more interesting elements of the K-machine architecture."

"The K-machine was designed in late 1985 - early 1986 and the first instructions were executed December 31, 1986. The hardware was significantly debugged by April 1986 and an effort to port the legacy Lisp Machine code to the K-machine was underway. The K-machine is designed to run Lisp, and Lisp only. As a result, the performance of the K-machine on the Gabriel benchmarks is significantly higher than that of any of the several contemporary competing products of the mid-to-late 1980's, among them the TI Explorer chip, the Symbolics Ivory, and Lucid Common Lisp. In fact, the K-machine was competitive with Lisp implementations on the Cray 1 and the IBM 3670. Financial difficulties kept the K-machine from reaching the marketplace."

Four stage pipeline; data layout is a 6-bit tag and a 26-bit word pointer, in a 32-bit word.

Architectural Principles
In any processor design there are fundamental "principles" from which the rest of the architecture derives. For the LMI K-machine, these were as follows:
    Optimistic instruction execution (execute based on assumptions, abort and retry if not holding - avoids type lookup to dispatch)
    Fully type-safe operation
    Non-expert user assumption
    32-bit objects (compared to 36 bit, lose some flexibility, but implementation is easier)
    RISC-like architecture (not strict RISC, not only simple instructions, but no multi-cycle instructions)
    50ns clock cycle (target - actual was 80ns)
    3-address machine (as opposed to a stack machine; necessitates 64 bit instructions)
    No CDR codes (performance cost and not often enough used, so 2 bits repurposed)
    "Level" implementation technology (all CMOS and TTL, to ensure possible upgrade)

via Dragonfly Digest

Thu Dec 06, 2018 3:01 pm
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