An interesting design - utilising heavily upon the availability of large ROMS
The ALU is implemented using a M27C322 2Mx16 bit EPROM and the decode logic is performed using a M27C1024 64K x 16 EEPROM.
https://processmodeling.org/theory/elec ... 27C322.pdfThis is in a 42 pin DIP and will require a special eprom programmer and adaptor socket to program - which may be a limiting factor to some home constructors.
The access time of the large ROM used in the ALU is 80nS which will be a limiting factor to the clock frequency. Similarly the decode logic ROM has at best a 45nS access time.
Nevertheless, the design shows how an 8 bit Von Neumann architecture can be implemented in a handful of TTL devices and four large memory chips.
The project detail, including devices used, instruction set etc can be found from this link:
https://github.com/DoctorWkt/CSCvon8/bl ... _design.md