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 far addressing on the pdp-11 
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1280
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(I've just made up the term far addressing.) Reading a discussion about how the PDP-11 might work in the absence of an MMU when executing four specific instructions, it seemed like an interesting idea: the regular program and data run in the usual 16 bit address space, and then when these specific instructions are used, two extra bits of high address are brought into play, these coming from the status word.

So, in a machine with a status word that has one or a few spare bits, one could use this idea to allow for load and store from an extended addressing range, without otherwise perturbing or extending the CPU design. If following the PDP-11 idea, that would be a far load and a far store operation. Or, possibly, a pair of loads and stores, accessing one or another segment of far memory, if perhaps there's room for two extension fields in the PSW.

Here's the discussion:
https://retrocomputing.stackexchange.co ... ory-withou


Thu Oct 03, 2019 2:33 pm
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