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 [ 2 posts ] 
 Different ways to talk about CPUs 
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1647
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It struck me that there are different ways to approach a CPU design - that is, to approach what it is, from the outside, given that the design already exists. And maybe those different ways also relate to doing the design, and indeed to communicating it to others.

Bearing in mind that each of us have different ways of apprehending the world, whether we be more verbal or more visual, or whatever, these different ways might each have a different level of appeal. It might be that a fully satisfactory explanation of a CPU includes all of these elements.

Anyhow, here's my take. I like lists, so here's a list of some possible ways:
- Describe the overall approach of the CPU: is it accumulator based, does it have specialised registers or a file of general purpose registers? Does it support more than one datatype? Are instructions variable length? Variable timing?
- Describe the programmer's model, perhaps with a diagram: show the available accumulators, registers, flags, and so on. They might have varied alignment or different sizes, in the case of segment or bank registers, or a short stack pointer, and so on.
- List the available operations, perhaps in families such as logical, arithmetic, control flow, and the available addressing modes, if any.
- Show the instruction set encoding, especially if it's regular or if it has two or three different formats. How many bytes or words to an instruction? How do they relate? What bitfields are there in each format? How are the formats identified?
- Show the implementation, as a block diagram. Show the various functional units, the internal busses. Where are the clock boundaries? What pipelining stages?
- Show the code: some HDL, or a HLL emulator. Consider if it's modular or monolithic, well-commented or otherwise, compact or otherwise. If there's microcode, that might be structured, commented, logically grouped, or otherwise.

There might well be other ways... discussion and ideas welcome!


Wed Jun 10, 2020 3:33 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 273
Architecture model is another way.
One , two or three addresses, stack , register, load store,OISC,other.
I tend to favor one address mode (direct+base indexing) plus immedate.
Memory types are a factor, like paper tape,magnetic drum,delayline,CRT,magnetic core,
mechanical,dram,static ram,on chip,relay.
Ben.


Wed Jun 10, 2020 6:32 pm
 [ 2 posts ] 

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