Last visit was: Sat Jul 13, 2024 9:02 am
It is currently Sat Jul 13, 2024 9:02 am

 [ 2 posts ] 
 Design process blog: A Bug-Free RISC-V Core (no Simulation) 
Author Message

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1789
worth a read. Using formal methods and the RISC-V testsuite. Tackling a simple machine first, but with some thinking ahead, with the aim of hitting reasonable performance: ... ation.html

A very different kind of debugging progress compared to the usual approach using simulation - and overall more time-efficient, I reckon. But, you do need the testsuite, which in the case of RISC-V has been written for you, and in the case of a homebrew CPU that would be a major task with its own kind of expertise.

Mon Jun 22, 2020 7:12 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 613
How ever formal logic still cannot stop simple typo or logic errors.
Working a on cross compiler with two versions, I had a output print out of
130 pages with only two typo errors. 1 #define BPW 4 rather than the
correct #define BPW 2 for that machine and forgotton & for &p->name[0]

Mon Jun 22, 2020 10:15 pm
 [ 2 posts ] 

Who is online

Users browsing this forum: CCBot and 0 guests

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Jump to:  
Powered by phpBB® Forum Software © phpBB Group
Designed by ST Software